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EM637327Q-8 Schematic ( PDF Datasheet ) - Etron Technology Inc.

Teilenummer EM637327Q-8
Beschreibung 1Mega x 32 SGRAM
Hersteller Etron Technology Inc.
Logo Etron Technology  Inc. Logo 




Gesamt 70 Seiten
EM637327Q-8 Datasheet, Funktion
EtronTech
Features
Fast access time from clock: 4.5/5.5/5.5/6 ns
Fast clock rate: 200/166/143/125 MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks (512K x 32bit x 2bank)
Programmable Mode
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
Single +3.3V ± 0.3V power supply
Interface: LVTTL
JEDEC 100-pin Plastic package
- QFP (body thickness=2.8mm)
- TQFP1.4 (body thickness=1.4mm)
Key Specifications
EM637327
tCK3 Clock Cycle time(min.)
tRAS Row Active time(max.)
tAC3 Access time from CLK(max.)
tRC Row Cycle time(min.)
- 5/6/7/8
5/6/7/8 ns
25/30/35/40 ns
4.5/5.5/5.5/6 ns
55/60/63/72 ns
Ordering Information
Part Number
EM637327Q-5
EM637327TQ-5
EM637327Q-6
EM637327TQ-6
EM637327Q-7
EM637327TQ-7
EM637327Q-8
EM637327TQ-8
Frequency
200 MHz
200 MHz
166 MHz
166 MHz
143 MHz
143 MHz
125 MHz
125 MHz
Package
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
QFP
TQFP1.4
EM637327
1Mega x 32 SGRAM
Preliminary (08/99)
Pin Assignment (Top View)
DQ 3
VDDQ
DQ 4
DQ 5
VSSQ
DQ 6
DQ 7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
WE#
CA S#
RA S#
CS 0#
BS
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80 DQ28
7 9 VDDQ
78 DQ27
77 DQ26
7 6 VSSQ
75 DQ25
74 DQ24
7 3 VDDQ
72 DQ15
71 DQ14
7 0 VSSQ
69 DQ13
68 DQ12
6 7 VDDQ
6 6 VSS
65 VDD
64 DQ11
63 DQ10
6 2 VSSQ
6 1 DQ 9
6 0 DQ 8
5 9 VDDQ
5 8 NC
57 DQM3
56 DQM1
5 5 CL K
5 4 CKE
53 DSF
5 2 NC
5 1 A8 (AP)
Overview
The EM637327 SGRAM is a high-speed CMOS
synchronous graphics DRAM containing 32 Mbits. It is
internally configured as a dual 512K x 32 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Each of the
512K x 32 bit banks is organized as 2048 rows by 256
columns by 32 bits. Read and write accesses to the
SGRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of a BankActivate command which
is then followed by a Read or Write command.
The EM637327 provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy
to use.
By having a programmable mode register, the
system can choose the most suitable modes to
maximize its performance. These devices are well
suited for applications requiring high memory
bandwidth.
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.






EM637327Q-8 Datasheet, Funktion
EtronTech
1Mega x 32 SGRAM EM637327
Commands
1 BankActivate & Masked Write Disable command
(RAS# = "L", CAS# = "H", WE# = "H", DSF = "L", BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal.
By latching the row address on A0 to A9 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.)
from the time of bank activation. A subsequent BankActivate command to a different row in the
same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SGRAM has two internal banks on the same chip and
shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of both banks. tRRD(min.) specifies the minimum time required between activating
different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.
T0 T1
T2 T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
..............
ADDRESS
C OM M A ND
Bank A
Row Addr.
RAS# - CAS# delay (tRCD)
Bank A
Activate
NOP
NOP
Bank A
Col Addr.
..............
Bank B
Row Addr.
Bank A
Row Addr.
RAS# - RAS# delay time (tRRD)
R/W A with
AutoPrecharge
..............
RAS# Cycle time (tRC)
Bank B
Activate
NOP
NOP
Bank A
Activate
: "H" or "L"
AutoPrecharge
Begin
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2 BankActivate & Masked Write Enable command (refer to the above figure)
(RAS# = "L", CAS# = "H", WE# = "H", DSF = "H", BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this
command is performed, the Write command and the Block Write command perform the masked
write operation. In the masked write and the masked block write functions, the I/O mask data that
was stored in the write mask register is used.
3 BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Bank, A8 = "L", A0-A7, A9-A10 = Don't care)
The BankPrecharge command precharges the bank disignated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
4 PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Don't care, A8 = "L", A0-A7, A9-A10 = Don't
care)The PrechargeAll command precharges both banks simultaneously and can be issued even if
both banks are not in the active state. Both banks are then switched to the idle state.
5 Read command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A8 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
Preliminary
6 August 1999

6 Page









EM637327Q-8 pdf, datenblatt
EtronTech
1Mega x 32 SGRAM EM637327
registered coincident with the Block Write command is used to mask specific column/byte
combinations within the block. The mapping of the DQ inputs to the column/byte combinations is
shown in following table.
The overall Block Write mask consists of a combination of the DQM inputs, the Mask register,
and the column/byte mask information, as shown in the following figure. The DQM and Mask
register masking operates normally as for a Write command, with the exception that the mask
information is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is
written only if a "0" is registered for the corresponding DQM input, a "1" is registered for the
corresponding DQ signal, and the corresponding bit in the Mask register is "1".
Block of Columns
(selected by A3-A7 registered
coincident with Block Write command)
Row in Bank
(selected by A0-A9,
and BS registered
coincident with BankActivate
Command)
Column Mask DQ0
on the DQ DQ1
inputs DQ2
(registered DQ3
DQ4
coincident DQ5
with Block DQ6
Write Command DQ7
DSF
BanckoAmctmivaanted
DQ
CK
MR0
Mask Register
(previously loaded
from corresponding
DQ inputs)
MR 1
MR2
MR3
MR4
MR5
MR6
MR7
DQM0
Note: Only the lower byte is shown. The operation is identical for other bytes.
Block-Write Masking Block Diagram
Preliminary
12 August 1999

12 Page





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