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EM636327TQ-8 Schematic ( PDF Datasheet ) - Etron Technology Inc.

Teilenummer EM636327TQ-8
Beschreibung 512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
Hersteller Etron Technology Inc.
Logo Etron Technology  Inc. Logo 




Gesamt 70 Seiten
EM636327TQ-8 Datasheet, Funktion
EtronTech
EM636327
512K x 32 High Speed Synchronous Graphics DRAM(SGRAM)
Preliminary (12/98)
Features
Fast access time from clock: 5/5/5.5/6.5/7.5 ns
Fast clock rate: 183/166/143/125/100 MHz
Fully synchronous operation
Internal pipelined architecture
Dual internal banks(256K x 32-bit x 2-bank)
Programmable Mode and Special Mode registers
- CAS# Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst-Read-Single-Write
- Load Color or Mask register
Burst stop function
Individual byte controlled by DQM0-3
Block write and write-per-bit capability
Auto Refresh and Self Refresh
2048 refresh cycles/32ms
Single +3.3V±0.3V power supply
Interface: LVTTL
JEDEC 100-pin Plastic package
-QFP (body thickness=2.8mm)
-TQFP1.4 (body thickness=1.4mm)
-TQFP1.0 (body thickness=1.0mm)
Overview
The EM636327 SGRAM is a high-speed
CMOS synchronous graphics DRAM containing 16
Mbits. It is internally configured as a dual 256K x
32 DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock
signal, CLK). Each of the 256K x 32 bit banks is
organized as 1024 rows by 256 columns by 32 bits.
Read and write accesses to the SGRAM are burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in
a programmed sequence. Accesses begin with the
registration of a BankActivate command which is
then followed by a Read or Write command.
The EM636327 provides for programmable
Read or Write burst lengths of 1, 2, 4, 8, or full
Key Specifications
EM636327
- 55/6/7/8/10
tCK3 Clock Cycle time(min.)
5.5/6/7/8/10 ns
tRAS Row Active time(max.)
32/36/42/48/60 ns
tAC1 Access time from Read command 7/8/13/18/23 ns
tAC3 Access time from CLK(max.)
5/5/5.5/6.5/7.5 ns
tRC Row Cycle time(min.)
48/54/63/72/90 ns
Ordering Information
Part Number Frequency Package
EM636327Q-10
100MHz
QFP
EM636327R-10
100MHz QFP (Reverse)
EM636327TQ-10 100MHz
TQFP1.4
EM636327JT-10
100MHz
TQFP1.0
EM636327Q-8
125MHz
QFP
EM636327R-8
125MHz QFP (Reverse)
EM636327TQ-8
125MHz
TQFP1.4
EM636327JT-8
125MHz
TQFP1.0
EM636327Q-7
143MHz
QFP
EM636327TQ-7
143MHz
TQFP1.4
EM636327Q-6
166MHz
QFP
EM636327TQ-6
166MHz
TQFP1.4
EM636327Q-55
183MHz
QFP
EM636327TQ-55 183MHz
TQFP1.4
page, with a burst termination option. An auto
precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end
of the burst sequence. The refresh functions,
either Auto or Self Refresh are easy to use. In
addition, EM636327 features the write-per-bit and
the masked block write functions.
By having a programmable mode register and
special mode register, the system can choose the
most suitable modes to maximize its performance.
These devices are well suited for applications
requiring high memory bandwidth, and when
combined with special graphics functions result in
a device particularly well suited to high
performance graphics applications.
Etron Technology, Inc.
1F, No. 1, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C
TEL: (886)-3-5782345 FAX: (886)-3-5779001
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.






EM636327TQ-8 Datasheet, Funktion
EtronTech
EM636327
Commands
1 BankActivate & Masked Write Disable command
(RAS# = "L", CAS# = "H", WE# = "H", DSF = "L", BS = Bank, A0-A9 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal.
By latching the row address on A0 to A9 at the time of this command, the selected row access is
initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.)
from the time of bank activation. A subsequent BankActivate command to a different row in the
same bank can only be issued after the previous active row has been precharged (refer to the
following figure). The minimum time interval between successive BankActivate commands to the
same bank is defined by tRC(min.). The SGRAM has two internal banks on the same chip and
shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back
activation of both banks. tRRD(min.) specifies the minimum time required between activating
different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.
T0 T1
T2 T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
..............
ADDRESS
C OM M A ND
Bank A
Row Addr.
RAS# - CAS# delay (tRCD)
Bank A
Activate
NOP
NOP
Bank A
Col Addr.
..............
Bank B
Row Addr.
Bank A
Row Addr.
RAS# - RAS# delay time (tRRD)
R/W A with
AutoPrecharge
..............
RAS# Cycle time (tRC)
Bank B
Activate
NOP
NOP
Bank A
Activate
: "H" or "L"
AutoPrecharge
Begin
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2 BankActivate & Masked Write Enable command (refer to the above figure)
(RAS# = "L", CAS# = "H", WE# = "H", DSF = "H", BS = Bank, A0-A9 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this
command is performed, the Write command and the Block Write command perform the masked
write operation. In the masked write and the masked block write functions, the I/O mask data that
was stored in the write mask register is used.
3 BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Bank, A9 = "L", A0-A8 = Don't care)
The BankPrecharge command precharges the bank disignated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed
in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle
state and is ready to be activated again.
4 PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", DSF = "L", BS = Don't care, A9 = "H", A0-A8 = Don't care)
The PrechargeAll command precharges both banks simultaneously and can be issued even if
both banks are not in the active state. Both banks are then switched to the idle state.
5 Read command
(RAS# = "H", CAS# = "L", WE# = "H", DSF = "L", BS = Bank, A9 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active
row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is
issued. During read bursts, the valid data-out element from the starting column address will be
available following the CAS# latency after the issue of the Read command. Each subsequent data-
out element will be valid by the next positive clock edge (refer to the following figure). The DQs go
Preliminary
6 December 1998

6 Page









EM636327TQ-8 pdf, datenblatt
EtronTech
EM636327
registered coincident with the Block Write command is used to mask specific column/byte
combinations within the block. The mapping of the DQ inputs to the column/byte combinations is
shown in following table.
The overall Block Write mask consists of a combination of the DQM inputs, the Mask register,
and the column/byte mask information, as shown in the following figure. The DQM and Mask
register masking operates normally as for a Write command, with the exception that the mask
information is applied simultaneously to all eight columns. Therefore, in a Block Write, a given bit is
written only if a "0" is registered for the corresponding DQM input, a "1" is registered for the
corresponding DQ signal, and the corresponding bit in the Mask register is "1".
Block of Columns
(selected by A3-A7 registered
coincident with Block Write command)
Row in Bank
(selected by A0-A9,
and BS registered
coincident with BankActivate
Command)
Column Mask DQ0
on the DQ DQ1
inputs DQ2
(registered DQ3
DQ4
coincident DQ5
with Block DQ6
Write Command DQ7
DSF
BanckoAmctmivaanted
DQ
CK
MR0
Mask Register
(previously loaded
from corresponding
DQ inputs)
MR 1
MR2
MR3
MR4
MR5
MR6
MR7
DQM0
Note: Only the lower byte is shown. The operation is identical for other bytes.
Block-Write Masking Block Diagram
Preliminary
12 December 1998

12 Page





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