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EL5485CS Schematic ( PDF Datasheet ) - Elantec Semiconductor

Teilenummer EL5485CS
Beschreibung Quad 4ns High Speed Comparators
Hersteller Elantec Semiconductor
Logo Elantec Semiconductor Logo 




Gesamt 12 Seiten
EL5485CS Datasheet, Funktion
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Features
• 4ns typ. propagation delay
• 5V to 12V input supply
• +2.7V to +5V output supply
• True-to-ground input
• Rail-to-rail outputs
• Separate analog and digital
supplies
• Active low latch
• Single (EL5185C) available
• Dual (EL5285C) available
• Window available (EL5287C)
• Pin-compatible 8ns family
available (EL5x81C, EL5283C &
EL5482C)
Applications
• Threshold detection
• High speed sampling circuits
• High speed triggers
• Line receivers
• PWM circuits
• High speed V/F converters
Ordering Information
Part No
EL5485CS
EL5485CS-T7
EL5485CS-T13
EL5486CU
EL5486CU-T13
Package
16-Pin SO
16-Pin SO
16-Pin SO
24-Pin QSOP
24-Pin QSOP
Tape & Reel
-
7”
13”
-
13”
Outline #
MDP0027
MDP0027
MDP0027
MDP0040
MDP0040
General Description
The EL5485C and EL5486C comparators are designed for operation
in single supply and dual supply applications with 5V to 12V between
VS+ and VS-. For single supplies, the inputs can operate from 0.1V
below ground for use in ground sensing applications.
The output side of the comparators can be supplied from a single sup-
ply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5485C and EL5486C can be used to hold the
comparator output value by applying a low logic level to the pin.
The EL5485C is available in the 16-pin SO package and the EL5486C
in the 24-pin QSOP package. Both are specified for operation over the
full -40°C to +85°C temperature range. Also available are single
(EL5185C), dual (EL5285C), and window comparator (EL5287C)
versions.
Pin Configurations
INA- 1
INA+ 2
GND 3
+-
OUTA 4
OUTB 5
VS- 6
INB+ 7
+-
INB- 8
16 IND-
15 IND+
-+
14 VS+
13 OUTD
12 OUTC
11 VSD
-+
10 INC+
9 INC-
EL5485CS
(16-Pin SO)
INA- 1
INA+ 2
NC 3
GND 4
+-
LATCHA 5
OUTA 6
OUTB 7
LATCHB 8
VS- 9
NC 10
+-
INB+ 11
INB- 12
24 IND-
23 IND+
22 NC
-+
21 VS+
20 LATCHD
19 OUTD
18 OUTC
17 LATCHC
16 VSD
-+
15 NC
14 INC+
13 INC-
EL5486CU
(24-Pin QSOP)
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2001 Elantec Semiconductor, Inc.






EL5485CS Datasheet, Funktion
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
Timing Diagram
Latch
Enable
Input
Latch
Differential
Input
Voltage
VIN
Comparator
Output
Compare
ts th
VOD
tpd-
Latch
Compare
tpw(D)
Latch
1.4V
VOS
td+
2.4V
Definition of Terms
Term
VOS
VIN
VOD
tpd+
tpd-
td+
td-
ts
th
tpw (D)
Definition
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
6

6 Page









EL5485CS pdf, datenblatt
EL5485C, EL5486C - Preliminary
Quad 4ns High Speed Comparators
General Disclaimer
Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the cir-
cuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described
herein and makes no representations that they are free from patent infringement.
Elantec Semiconductor, Inc.
675 Trade Zone Blvd.
Milpitas, CA 95035
Telephone: (408) 945-1323
(888) ELANTEC
Fax: (408) 945-9305
European Office: +44-118-977-6020
Japan Technical Center: +81-45-682-5820
WARNING - Life Support Policy
Elantec, Inc. products are not authorized for and should not be used
within Life Support Systems without the specific written consent of
Elantec, Inc. Life Support systems are equipment intended to sup-
port or sustain life and whose failure to perform when properly used
in accordance with instructions provided can be reasonably
expected to result in significant personal injury or death. Users con-
templating application of Elantec, Inc. Products in Life Support
Systems are requested to contact Elantec, Inc. factory headquarters
to establish suitable terms & conditions for these applications. Elan-
tec, Inc.’s warranty is limited to replacement of defective
components and does not cover injury to persons or property or
other consequential damages.
12 Printed in U.S.A.

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