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EL5281CS-T7 Schematic ( PDF Datasheet ) - Elantec Semiconductor

Teilenummer EL5281CS-T7
Beschreibung Dual 8ns High-Speed Comparator
Hersteller Elantec Semiconductor
Logo Elantec Semiconductor Logo 




Gesamt 11 Seiten
EL5281CS-T7 Datasheet, Funktion
EL5281C
Dual 8ns High-Speed Comparator
Features
• 8ns Typ. Propagation Delay
• 5V to 12V Input Supply
• +2.7V to +5V Output Supply
• True-to-ground Input
• Rail-to-rail Outputs
• Active Low Latch
• Single Available (EL5181C)
• Quad Available (EL5481C &
EL5482C)
• Pin-compatible 4ns Family
Available (EL5x85C, EL5287C &
EL5486C)
Applications
• Threshold Detection
• High Speed Sampling Circuits
• High Speed Triggers
• Line Receivers
• PWM Circuits
• High Speed V/F Converters
General Description
The EL5281C comparator is designed for operation in single supply
and dual supply applications with 5V to 12V between VS+ and VS-.
For single supplies, the inputs can operate from 0.1V below ground for
use in ground-sensing applications.
The output side of the comparator can be supplied from a single sup-
ply of 2.7V to 5V. The rail-to-rail output swing enables direct
connection of the comparator to both CMOS and TTL logic circuits.
The latch input of the EL5281C can be used to hold the comparator
output value by applying a low logic level to the pin. The EL5281C
features two separate comparators.
The EL5281C is available in the 14-pin SO package and is specified
for operation over the full -40°C to +85°C temperature range. Also
available are a single (EL5181C) and quad versions (EL5481C and
EL5482C).
Pin Configuration
Ordering Information
Part No.
EL5281CS
EL5281CS-T7
EL5281CS-T13
Package
14-Pin SO
14-Pin SO
14-Pin SO
Tape & Reel
-
7”
13”
Outline #
MDP0027
MDP0027
MDP0027
VS+ 1
INA+ 2
INA- 3
NC 4
INB+ 5
INB- 6
VS- 7
+
-
+
-
EL5281C
14-Pin SO
14 VSD
13 OUTA
12 LATCHA
11 NC
10 LATCHB
9 OUTB
8 GND
Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these
specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation.
© 2001 Elantec Semiconductor, Inc.






EL5281CS-T7 Datasheet, Funktion
EL5281C
Dual 8ns High-Speed Comparator
Timing Diagram
Latch
Enable
Input
Latch
Differential
Input
Voltage
VIN
Comparator
Output
Compare
ts th
VOD
tpd-
Latch
Compare
tpw(D)
Latch
1.4V
VOS
td+
2.4V
Definition of Terms
Terms
VOS
VIN
VOD
tpd+
tpd-
td+
td-
ts
th
tpw (D)
Definition
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output low to high transition
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS
logic threshold of an output high to low transition
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a low to high transition
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high
transition to the point of the output crossing CMOS threshold in a high to low transition
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in
order to be acquired and held at the outputs
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in
order to be acquired and held at the output
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal
change
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