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DM74ALS165 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer DM74ALS165
Beschreibung 8-Bit Parallel In/Serial Out Shift Register
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 6 Seiten
DM74ALS165 Datasheet, Funktion
January 1986
Revised February 2000
DM74ALS165
8-Bit Parallel In/Serial Out Shift Register
General Description
The DM74ALS165 is an 8-bit serial register that, when
clocked, shifts the data toward serial output, QH. Parallel-in
access to each stage is provided by eight individual direct
data inputs that are enabled by a low level at the SH/LD
input. The DM74ALS165 also features a clock inhibit func-
tion and a complemented serial output, QH.
Clocking is accomplished by a LOW-to-HIGH transition of
the CLK input while SH/LD is held HIGH and CLK INH is
held LOW. The functions of the CLK and CLK INH (clock
inhibit) inputs are interchangeable. Since a LOW CLK input
and a LOW-to-HIGH transition of CLK INH will also accom-
plish clocking, CLK INH should be changed to the high
level only while the CLK input is HIGH. Parallel loading is
inhibited when SH/LD is held HIGH. The parallel inputs to
the register are enabled while SH/LD is LOW indepen-
dently of the levels of CLK, CLK INH, or SER inputs.
Features
s Complementary outputs
s Direct overriding load (data) inputs
s Gated clock inputs
s Parallel-to-serial data conversion
Ordering Code:
Order Number Package Number
Package Description
DM74ALS165M
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74ALS165N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Internal
Shift/ Clock Clock Serial Parallel Outputs Output
Load Inhibit
A...H QA QB QH
L X X X a...h a b h
HL
LX
X QA0 QB0 QH0
HL
H
X H QAn QGn
HL L
X L QAn QGn
HLH
X H QAn QGn
HL L
X L QAn QGn
HH X X
X QA0 QB0 QH0
H = HIGH Level (steady-state),
L = LOW Level (steady-state)
X = Don't Care (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
a...h = The level of steady-state input at inputs A through H, respectively
QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the
indicated steady-state input conditions were established
QAn, QGn = The level of QA or QG, respectively, before the most recent
transition of the clock
© 2000 Fairchild Semiconductor Corporation DS006712
www.fairchildsemi.com






DM74ALS165 Datasheet, Funktion
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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