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DM6380L Schematic ( PDF Datasheet ) - ETC

Teilenummer DM6380L
Beschreibung V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
DM6380L Datasheet, Funktion
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
General Description
The DM336P integrated modem is a four chipset
design that provides a complete solution for state-of-
the-art, voice-band Plain Old Telephone Service
(POTS) communication. The modem provides for
Data (up to 33,600bps), Fax (up to 14,400bps), Voice
and Full Duplex Speaker-phone functions to comply
with various international standards.
The design of the DM336P is optimized for desktop
personal computer applications and it provides a low
cost, highly reliable, maximum integration, with the
minimum amount of support required. The DM336P
modem can operate over a dial-up network (PSTN) or
2 wire leased lines.
The modem integrates auto dial and answer
capabilities, synchronous and asynchronous data
transmissions, serial and parallel interfaces, various
tone detection schemes and data test modes.
The DM336P modem’s reference design is pre-
approved for FCC part 68 and provides minimum
design cycle time, with minimum cost to insure the
maximum amount of success.
The simplified modem system, shown in figure below,
illustrates the basic interconnection between the
MCU, DSP, AFE and other basic components of a
modem. The individual elements of the DM336P are:
• DM6380 Analog Front End (AFE). 28-pin PLCC
package
• DM6381 ITU-T V.34 Transmit Digital Signal
Processor (TX DSP). 100-pin QFP package
• DM6382 ITU-T V.34 Receive Digital Signal
Processor (RX DSP). 100-pin QFP package
• DM6383 Modem Controller (MCU) built in Plug &
Play (PnP). 100-pin QFP package
Block Diagram
ISA Bus
LED
Ring
Detector
‘‰†‹†
Micro
Controller
Unit
PnP
V.24
Interface
V.24
Interface
Address &
Data Bus
MSCLK
‘‰†‹„
TX DSP
‘‰†‹…
TxD
RxD
RX DSP
40.32MHz
SCLK
DIT
DOT
TFS
DIR
DOR
RFS
TxBCLK
TxSCLK*2
RxBCLK
RxSCLK
20.16MHz
TxDCLK
RxDCLK
‘‰†‹ƒ RxIN
TxA1 DAA
Analog TxA2
Font End
Speaker
SPKR
Driver
Line
Microphone
Driver
Final
Version: DM336P-DS-F02
August 15, 2000
1






DM6380L Datasheet, Funktion
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
DM6383 Pin Description
Pin No.
Pin Name
I/O
Description
1-8
UD0 - UD7
I/O Data Bus Signal, in internal modem:
These signals are connected to the data bus of the PC I/O slot.
They are used to transfer data between the PC and the DM6383.
Modem Control Output, in external Modem:
Memory address mapping of the controller is E800H.
9
/IOR
I I/O Read:
An active low signal used to read data from the DM6383.
10
GND
P Ground
11
/IOW
I I/O Write:
An active low signal used to write data to DM6383.
12
/AEN
I Address Enable:
This is an active low signal to enable the system address for
DM6383.
13 - 24
A11 - A0
I System Address:
These signals are connected to the bus of PC I/O slot. They are
used to select DM6383 I/O ports.
25, 36, 52,
VDD
P +5V Power Supply
100
26, 27, 28, IRQ4, IRQ5,
O Interrupt Request:
29, 33 - 35 IRQ7, IRQ10,
These are 8 interrupt request pins. Only one pin, which is decoded
IRQ11, IRQ12,
from Configuration Register, can be activated, the other pins are
IRQ15
left floating. The active pin will go high when an interrupt request is
generated from the DM6383.
30
RESET
I Reset:
An active high signal used to power-on reset the DM6383.
31
XTAL1
I Crystal Oscillator Input
32
XTAL2
O Crystal Oscillator Output
37
TEST2
I Test Pin (see description of pin 99)
38
EAB/VP
I External ROM Select:
Should be connected to low state.
39
/RUCS
O RX DSP Register Select Output:
Memory address mapping of the controller is E400H.
40
CA16
O Bank Switch Control:
This signal is used to switch external program memory between
bank 0 (lower 64K bytes) and bank 1 (upper 64K bytes) when the
EPROM for system use is 27010 (128Kx8 bits). Otherwise, this pin
is not connected.
41, 68, 85, 96
GND
P Ground
42 T0 I Controller Counter 0 Input
43 T1 I Controller Counter 1 Input
44 /RI I Ring Signal Input
45, 46,
P1.1, P1.2,
I/O Controller Port 1 I/O
48 - 51
P1.4 - P1.7
6 Final
Version: DM336P-DS-F02
August 15, 2000

6 Page









DM6380L pdf, datenblatt
DM336P
V.34 Integrated Data/ Fax/Voice/Speakerphone Modem Device Set
f. Modem Control Register (MCR): Address 4
Reset State 00h
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0 0 0 0 0 0 RTS DTR
Bit 0: This bit asserts a Data Terminal Ready
condition that is readable via port P1.1 of micro-
controller 8031. When bit 0 is set to logic 1, the
P1.1 is forced to logic 0. When bit 0 is reset to
logic 0, the P1.1 is forced to logic 1.
Bit 1: This bit asserts a Request To Send condition
that is readable via port P3.4 of the micro-
controller 8031. Bit 1 affects P3.4 in a manner
identical to that described above for bit 0.
g. Line Status Register (LSR): Address 5
Reset State 60h, Read only
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
RCV ETEMT THRE BI FE PE OE DR
This register provides status information to the host
PC concerning the data transfer. Bit 1-4 indicate the
error conditions that produce a Receiver Line Status
interrupt whenever any of the corresponding
conditions are detected. The Line Status Register is
intended for read operations only.
Bit 0: Set to logic 1 when a received character is
available in the RxFIFO. This bit is reset to logic
0 when the RxFIFO is empty.
Bit 1: An Overrun error will occur only after the
RxFIFO is full and the next character has
overwritten the unread FIFO data. This bit is
reset upon reading the Line Status Register.
Bit 2: A value of logic 1 indicates that a received
character does not have the correct even or
odd parity as selected by the Even Parity Select
bit. This error is set when the corresponding
character is at the top of the RxFIFO. It will
remain set until the CPU reads the LSR. This
Parity Error indication is associated with the
particular character in the FIFO to which it
applies. This error is revealed to the CPU when
its associated character is at the top of the
FIFO.
Bit 3: This bit is the Framing Error (FE) indicator. Bit 3
indicates that the received character did not
have a valid stop bit. Bit 3 is set to a logic 1
whenever the stop bit following the last data bit
or parity bit is detected as a zero bit (spacing
level). The FE bit is reset whenever the CPU
reads the contents of the Line Status Register.
The FE error condition is associated with the
particular character in the FIFO to which it
applies. This error is revealed to the CPU when
its associated character is at the top of the
FIFO.h. Modem Status Register (MSR):
Address 6 Reset State, bit 0-3: low, bit 4-7:
input signal.
Bit 4: This bit is a Break Interrupt (BI) indicator. Bit 4
is set to logic 1 whenever the received data
input is held in the Spacing (logic 0) state for
longer than a full word transmission time (that is,
the total time of Start bit + data bits + Parity +
Stop bits). The BI indicator is reset whenever
the CPU reads the contents of the Line Status
Register. The BI error condition is associated
with the particular character in the FIFO to
which it applies. This error is revealed to the
CPU when its associated character is at the top
of the FIFO.
Bit 5: This bit is a Transmitter Holding Register Empty
indicator. Bit 5 indicates that UART is ready to
accept a new character for transmission. In
addition, this bit causes UART to issue an
interrupt to the CPU when the Transmit Holding
Register Empty Interrupt Enable is set high. The
THRE bit is reset to logic 0 when the host CPU
loads a character into the Transmit Holding
register. In the FIFO mode, this bit is set when
the TxFIFO is empty, and is cleared when at
least 1 byte is written to the TxFIFO.
Bit 6: This bit is the Transmitter Empty indicator. Bit 6
is set to a logic 1 whenever the Transmitter
Holding Register (THR) is empty, and is reset to
a logic 0 whenever the THR contains a
character. In FIFO mode, this bit is set to 1
whenever the transmitter FIFO is empty.
Bit 7: In character mode, this bit is 0. In FIFO mode,
this bit is set when there is at least one parity
error, framing error, or break indication in the
FIFO. If there are no subsequent errors in the
FIFO, LSR7 is cleared when the CPU reads the
LSR.
12 Final
Version: DM336P-DS-F02
August 15, 2000

12 Page





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