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PDF DM54LS181 Data sheet ( Hoja de datos )
| Número de pieza | DM54LS181 | |
| Descripción | 4-Bit Arithmetic Logic Unit | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1992
DM54LS181 DM74LS181
4-Bit Arithmetic Logic Unit
General Description
The ’LS181 is a 4-bit Arithmetic Logic Unit (ALU) which can
perform all the possible 16 logic operations on two variables
and a variety of arithmetic operations
Features
Y Provides 16 arithmetic operations add subtract com-
pare double plus twelve other arithmetic operations
Y Provides all 16 logic operations of two variables exclu-
sive-OR compare AND NAND OR NOR plus ten
other logic operations
Y Full lookahead for high speed arithmetic operation on
long words
Connection Diagram
Dual-In-Line Package
TL F 9821 – 1
Order Number DM54LS181J DM54LS181W or DM74LS181N
See NS Package Number J24A N24A or W24C
Pin Names
A0 – A3
B0 – B3
S0 – S3
M
Cn
F0– F3
AeB
G
P
Cna4
Description
Operand Inputs (Active LOW)
Operand Inputs (Active LOW)
Function Select Inputs
Mode Control Input
Carry Input
Function Outputs (Active LOW)
Comparator Output
Carry Generate Output (Active LOW)
Carry Propagate Output (Active LOW)
Carry Output
C1995 National Semiconductor Corporation TL F 9821
RRD-B30M115 Printed in U S A
1 page  
Logic Mode Test Table III Function Inputs S1 e S2 e M e 4 5V S0 e S3 e 0V
Symbol
tPLH
tPHL
tPLH
tPHL
Input
Under
Test
A
B
Other Input
Same Bit
Apply
4 5V
Apply
GND
B None
A None
Other Data Inputs
Apply
4 5V
None
None
Apply
GND
Remaining
A and B Cn
Remaining
A and B Cn
Output
Under
Test
Any F
Any F
Functional Description
The ’LS181 is a 4-bit high speed parallel Arithmetic Logic
Unit (ALU) Controlled by the four Function Select inputs
(S0 – S3) and the Mode Control input (M) it can perform all
the 16 possible logic operations or 16 different arithmetic
operations on active HIGH or active LOW operands The
Function Table lists these operations
When the Mode Control input (M) is HIGH all internal car-
ries are inhibited and the device performs logic operations
on the individual bits as listed When the Mode Control input
is LOW the carries are enabled and the device performs
arithmetic operations on the two 4-bit words The device
incorporates full internal carry lookahead and provides for
either ripple carry between devices using the Cna4 output
or for carry lookahead between packages using the signals
P (Carry Propagate) and G (Carry Generate) In the ADD
mode P indicates that F is 15 or more while G indicates
that F is 16 or more In the SUBTRACT mode P indicates
that F is zero or less while G indicates that F is less than
zero P and G are not affected by carry in When speed
requirements are not stringent it can be used in a simple
ripple carry mode by connecting the Carry output (Cna4)
signal to the Carry input (Cn) of the next unit For high speed
operation the device is used in conjunction with the 9342 or
93S42 carry lookahead circuit One carry lookahead pack-
age is required for each group of four ’LS181 devices Carry
lookahead can be provided at various levels and offers high
speed capability over extremely long word lengths
The A e B output from the device goes HIGH when all four
F outputs are HIGH and can be used to indicate logic equiv-
alence over four bits when the unit is in the subtract mode
The A e B output is open-collector and can be wired-AND
with other A e B outputs to give a comparison for more
than four bits The A e B signal can also be used with the
Cna4 signal to indicate A l B and A k B
The Function Table lists the arithmetic operations that are
performed without a carry in An incoming carry adds a one
to each operation Thus select code LHHL generates A
minus B minus 1 (2s complement notation) without a carry
in and generates A minus B when a carry is applied Be-
cause subtraction is actually performed by complementary
addition (1s complement) a carry out means borrow thus a
carry is generated when there is no underflow and no carry
is generated when there is underflow As indicated this de-
vice can be used with either active LOW inputs producing
active LOW outputs or with active HIGH inputs producing
active HIGH outputs For either case the table lists the oper-
ations that are performed to the operands labeled inside the
logic symbol
Function Table
Mode Select
Inputs
Active LOW Operands
Fn Outputs
Logic
Arithmetic
S3 S2 S1 S0 (M e H) (M e L) (Cn e L)
L L L LA
A minus 1
L L L H AB
AB minus 1
L L H L AaB
AB minus 1
L L H H Logic 1 minus 1
L H L L AaB
L H L HB
L H H L AZB
L H H H AaB
A plus (A a B)
AB plus (A a B)
A minus B minus 1
AaB
H L L L AB
H L L H AZB
H L H LB
H L H H AaB
A plus (A a B)
A plus B
AB plus (A a B)
AaB
H H L L Logic 0
H H L H AB
H H H L AB
H H H HA
Each bit is shifted to the next most significant position
Arithmetic operations expressed in 2s complement notation
A plus A
AB plus A
AB minus A
A
5
Active HIGH Operands
Fn Outputs
Logic
(M e H)
Arithmetic
(M e L) (Cn e H)
A
AaB
AB
Logic 0
A
AaB
AaB
minus 1
AB
B
AZB
AB
A plus AB
(A a B) plus AB
A minus B minus 1
AB minus 1
AaB
AZB
B
AB
A plus AB
A plus B
(A a B) plus AB
AB minus 1
Logic 1
AaB
AaB
A
A plus A
(A a B) plus A
(A a B) plus A
A minus 1
5 Page | ||
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| PDF Descargar | [ Datasheet DM54LS181.PDF ] | |
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