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PDF DM54L95 Data sheet ( Hoja de datos )
| Número de pieza | DM54L95 | |
| Descripción | 4-Bit Parallel Access Shift Registers | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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June 1989
DM54L95 4-Bit Parallel Access Shift Registers
General Description
These 4-bit registers feature parallel and serial inputs paral-
lel output mode control and two clock inputs The registers
have three modes of operation
Parallel (broadside) load
Shift right (the direction QA toward QD)
Shift left (the direction QD toward QA)
Parallel loading is accomplished by applying the four bits of
data and taking the mode control input high The data is
loaded into the associated flip-flops and appears at the out-
puts after the high-to-low transition of the clock-2 input Dur-
ing loading the entry of serial data is inhibited
Shift right is accomplished on the high-to-low transition of
clock 1 when the mode control is low shift left is accom-
plished on the high-to-low transition of clock 2 when the
Connection Diagram
Dual-In-Line Package
mode control is high by connecting the output of each flip-
flop to the parallel input of the previous flip-flop (QD to input
C etc ) and serial data is entered at input D The clock input
may be applied simultaneously to clock 1 and clock 2 if both
modes can be clocked from the same source
Changes at the mode control input should normally be
made while both clock inputs are low however conditions
described in the last three lines of the truth table will also
ensure that register contents are protected
Features
Y Typical maximum clock frequency 14 MHz
Y Typical power dissipation mW
Order Number DM54L95J
or DM54L95W
See NS Package Number
J14A or W14B
Function Table
TL F 6638 – 1
Inputs
Outputs
Mode
Clocks
Serial
Control 2 (L) 1 (R)
A
Parallel
QA QB QC QD
B CD
H H X X X X X X QAO QBO QCO QDO
vH X X a b c d a b c d
vH X X QB QC QD d QBn QCn QDn d
L L H X X X X X QAO QBO QCO QDO
vL X
H X X X X H QAn QBn QCn
vL X
L X X X X L QAn QBn QCn
u L L X X X X X QAO QBn QCO QDO
v L L X X X X X QAO QBO QCO QDO
v L H X X X X X QAO QBO QCO QDO
u H L X X X X X QAO QBO QCO QDO
u H H X X X X X QAO QBO QCO QDO
Shifting left requires external connection of QB to A QC to B QD to C Serial data is entered at input D
H e High Level (Steady State) L e Low Level (Steady State) X e Don’t Care (Any input including transitions)
v ue Transition from high to low level e Transition from low to high level
a b c d e The level of steady state input at inputs A B C or D respectively
QAO QBO QCO QDO e The level of QA QB QC or QD respectively before the indicated steady state input conditions were established
vQAn QBn QCn QDn e The level of QA QB QC or QD respectively before the most recent transition of the clock
C1995 National Semiconductor Corporation TL F 6638
RRD-B30M105 Printed in U S A
1 page | ||
| Páginas | Total 4 Páginas | |
| PDF Descargar | [ Datasheet DM54L95.PDF ] | |
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