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EBS25UC8APMA-7AL Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBS25UC8APMA-7AL
Beschreibung 256MB SDRAM Micro DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 14 Seiten
EBS25UC8APMA-7AL Datasheet, Funktion
DATA SHEET
256MB SDRAM Micro DIMM
EBS25UC8APMA (32M words × 64 bits, 1 bank)
Description
The EBS25UC8APMA is 32M words × 64 bits, 1 bank
Synchronous Dynamic RAM Micro Dual In-line Memory
Module (Micro DIMM), mounted 8 pieces of 256M bits
SDRAM sealed in µBGApackage. This module
provides high density and large quantities of memory in
a small space without utilizing the surface mounting
technology. Decoupling capacitors are mounted on
power supply line for noise reduction.
Note : Do not push the cover or drop the modules in
order to protect from mechanical defects, which
would be electrical defects.
Features
Fully compatible with 8 bytes Micro DIMM: JEDEC
standard outline
144-pin socket type micro dual in line memory
module (Micro DIMM)
PCB height: 30.00mm (1.18inch )
Lead pitch: 0.50mm
3.3V power supply
Clock frequency: 100MHz/133MHz (max.)
LVTTL interface
Data bus width: × 64 non-ECC
Single pulsed /RAS
4 Banks can operates simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length (BL): 1, 2, 4, 8, Full page
2 variations of burst sequence
Sequential
Interleave
Programmable /CAS latency (CL): 2, 3
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
Document No. E0241E30 (Ver. 3.0)
Date Published May 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002






EBS25UC8APMA-7AL Datasheet, Funktion
EBS25UC8APMA
Block Diagram
/CS0
/WE
DQMB0
/CS
8 N0, N1
DQ0 to DQ7
D0
DQMB1
/CS
8 N8, N9
DQ8 to DQ15
D1
DQMB2
/CS
DQMB3
/CS
8 N2, N3
DQ16 to DQ23
D2
8 N10, N11
DQ24 to DQ31
D3
DQMB4
/CS
DQMB5
/CS
8 N4, N5
DQ32 to DQ39
D4
8 N12, N13
DQ40 to DQ47
D5
DQMB6
/CS
DQMB7
/CS
8 N6, N7
DQ48 to DQ55
D6
8 N14, N15
DQ55 to DQ64
D7
/RAS
/CAS
A0 to A12
BA0
BA1
CKE0
CLK0
VDD
VSS
CLK1
C100 to C118
10
/RAS (D0 to D7)
/CAS (D0 to D7)
A0 to A12 (D0 to D7)
BA0 (D0 to D7)
BA1 (D0 to D7)
CKE (D0 to D7)
CLK (D0 to D7)
VDD (D0 to D7)
VSS (D0 to D7)
10pF
Serial PD
SCL SCL SDA SDA
A0 U0
A1
A2
VSS
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
* D0 to D7: 256M bits SDRAM
U0: 2k bits EEPROM
C100 to C118: 0.1µF
N0 to N15: Network resistors (10)
Data Sheet E0241E30 (Ver. 3.0)
6

6 Page









EBS25UC8APMA-7AL pdf, datenblatt
Physical Outline
1.0 min.
EBS25UC8APMA
42.0 max.
(38.0)
1.0 min.
Unit: mm
3.80 max.
1
A
R1.0 ± 0.1
Component area
(front)
35.50
B
17.625
37.0 ± 0.08
35.50
17.875
0.875
0.625
0.80 ± 0.08
4-R1.0 ± 0.1
1.0 min.
Detail A
Component area
(back)
1.0 min.
Detail B
0.50
1.0 ± 0.08
0.37 ± 0.03
Data Sheet E0241E30 (Ver. 3.0)
12
ECA-TS2-0028-01

12 Page





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