EBS12UC6APS-7A Datasheet PDF - Elpida Memory
| Part Number | EBS12UC6APS-7A | |
| Description | 128MB SDRAM S.O.DIMM | |
| Manufacturers | Elpida Memory | |
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DATA SHEET
128MB SDRAM S.O.DIMM
EBS12UC6APS (16M words × 64 bits, 1 bank)
Description
The EBS12UC6APS is 16M words × 64 bits, 1 bank
Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 4 pieces of
256M bits SDRAM (EDS2516APTA) sealed in TSOP
package. This module provides high density and large
quantities of memory in a small space without utilizing
the surface mounting technology. Decoupling
capacitors are mounted on power supply line for noise
reduction.
Features
• Fully compatible with 8 bytes S.O.DIMM: JEDEC
standard outline
• 144-pin socket type small outline dual in line memory
module (S.O.DIMM)
PCB height: 31.75mm (1.25inch )
Lead pitch: 0.80mm
• 3.3V power supply
• Clock frequency: 100MHz/133MHz (max.)
• LVTTL interface
• Data bus width: × 64 non-ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, Full page
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0224E20 (Ver. 2.0)
Date Published November 2001 (K) Japan
URL: http://www.elpida.com
C Elpida Memory, Inc. 2001
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EBS12UC6APS
Byte No. Function described
28
Row active to row active min
(-7A/7AL, -75/75L)
(-80/80L)
29
/RAS to /CAS delay min
(-7A/7AL)
(-75/75L, -80/80L)
30
Minimum /RAS pulse width
(-7A/7AL, -75/75L)
(-80/80L)
31 Density of each bank on module
Address and command signal input
32 setup time
(-7A/7AL, -75/75L)
(-80/80L)
Address and command signal input
33 hold time
(-7A/7AL, -75/75L)
(-80/80L)
34
Data signal input setup time
(-7A/7AL, -75/75L)
(-80/80L)
35
Data signal input hold time
(-7A/7AL, -75/75L)
(-80/80L)
36 to 61 Superset information
62 SPD data revision code
63
Checksum for Bytes 0 to 62
(-7A/7AL)
(-75/75L)
(-80/80L)
64 Manufacturer’s JEDEC ID code
65 to 71 Manufacturer’s JEDEC ID code
72 Manufacturing location
73 to 90 Manufacturer’s part number
91 to 92 Revision code
93 to 94 Manufacturing date
95 to 98 Assembly serial number
99 to 125 Manufacturer specific data
126
Reserved (Intel specification
frequency)
127
Reserved (Intel specification /CAS#
latency support)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 0 0 0 10H
0 0 0 0 1 1 1 1 0FH
0 0 0 1 0 1 0 0 14H
0 0 1 0 1 1 0 1 2DH
0 0 1 1 0 0 0 0 30H
0 0 1 0 0 0 0 0 20H
0 0 0 1 0 1 0 1 15H
0 0 1 0 0 0 0 0 20H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 0 0 0 10H
0 0 0 1 0 1 0 1 15H
0 0 1 0 0 0 0 0 20H
0 0 0 0 1 0 0 0 08H
0 0 0 1 0 0 0 0 10H
0 0 0 0 0 0 0 0 00H
0 0 0 1 0 0 1 0 12H
0 1 1 1 1 0 0 0 78H
1 0 1 1 1 0 0 1 B9H
1 1 1 1 1 0 1 0 FAH
1 1 1 1 1 1 1 0 FEH
0 0 0 0 0 0 0 0 00H
0 1 1 0 0 1 0 0 64H
1 1 0 0 0 1 1 1 C7H
Comments
15ns
16ns
15ns
20ns
45ns
48ns
128MB
1.5ns
2ns
0.8ns
1ns
1.5ns
2ns
0.8ns
1ns
1.2
Elpida Memory
100MHz
Data Sheet E0224E20 (Ver. 2.0)
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for EBS12UC6APS-7A electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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