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Teilenummer | EBS12UC6APS |
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Beschreibung | 128MB SDRAM S.O.DIMM | |
Hersteller | Elpida Memory | |
Logo | ||
Gesamt 14 Seiten DATA SHEET
128MB SDRAM S.O.DIMM
EBS12UC6APS (16M words × 64 bits, 1 bank)
Description
The EBS12UC6APS is 16M words × 64 bits, 1 bank
Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 4 pieces of
256M bits SDRAM (EDS2516APTA) sealed in TSOP
package. This module provides high density and large
quantities of memory in a small space without utilizing
the surface mounting technology. Decoupling
capacitors are mounted on power supply line for noise
reduction.
Features
• Fully compatible with 8 bytes S.O.DIMM: JEDEC
standard outline
• 144-pin socket type small outline dual in line memory
module (S.O.DIMM)
PCB height: 31.75mm (1.25inch )
Lead pitch: 0.80mm
• 3.3V power supply
• Clock frequency: 100MHz/133MHz (max.)
• LVTTL interface
• Data bus width: × 64 non-ECC
• Single pulsed /RAS
• 4 Banks can operates simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, Full page
• 2 variations of burst sequence
Sequential
Interleave
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQMB
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
Document No. E0224E20 (Ver. 2.0)
Date Published November 2001 (K) Japan
URL: http://www.elpida.com
C Elpida Memory, Inc. 2001
EBS12UC6APS
Block Diagram
/WE
/CS0
DQMB0
DQ0 to DQ7
DQMB4
DQ32 to DQ39
/CS
8 N0, N1
D0
8 N2, N3
DQMB2
DQ16 to DQ23
DQMB6
DQ48 to DQ55
8 N8, N9
/CS
D2
8 N10, N11
DQMB1
DQ8 to DQ15
DQMB5
DQ40 to DQ47
/CS
8 N4, N5
D1
8 N6, N7
DQMB3
DQ24 to DQ31
DQMB7
DQ56 to DQ63
/CS
8 N12, N13
D3
8 N14, N15
/RAS
/CAS
A0 to A12
BA0
BA1
CKE0
CLK0
CLK1
VCC
VSS
10Ω
10pF
/RAS (D0 to D3)
/CAS (D0 to D3)
A0 to A12 (D0 to D3)
BA0 (D0 to D3)
BA1 (D0 to D3)
CKE (D0 to D3)
CLK (D0 to D3)
VCC (D0 to D3, U0)
C100-C123
VSS (D0 to D3, U0)
Serial PD
SCL SCL SDA SDA
A0 U0
A1
A2
VSS
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
* D0 to D3 : EDS2516AP
U0 : 2k bits EEPROM
C100 to C123 : 0.1µF
N0 to N15 : Network resistors (10Ω)
Data Sheet E0224E20 (Ver. 2.0)
6
6 Page Physical Outline
EBS12UC6APS
24.50
63.60
(Datum -A-)
2R3.00 Min
Unit:mm
3.80 Max
Component area
(front)
3.30
3.70
23.20
2.50
B
32.80
4.60
67.6 ± 0.15
A
2.10
23.20
4.60
32.80
1.00 ± 0.10
2- ø1.80
2-R2.00
Detail A
Component area
(back)
(Datum -A-)
0.60 ± 0.05
2.00 Min
Detail B
2.5
(DATUM -A-)
R0.75
0.80
1.50 ± 0.10
ECA-TS2-0047-01
Data Sheet E0224E20 (Ver. 2.0)
12
12 Page | ||
Seiten | Gesamt 14 Seiten | |
PDF Download | [ EBS12UC6APS Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
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