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EBD11UD8ABFB-6B Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EBD11UD8ABFB-6B
Beschreibung 1GB Unbuffered DDR SDRAM DIMM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 19 Seiten
EBD11UD8ABFB-6B Datasheet, Funktion
PRELIMINARY DATA SHEET
1GB Unbuffered DDR SDRAM DIMM
EBD11UD8ABFB (128M words × 64 bits, 2 Banks)
Description
The EBD11UD8ABFB is 128M words × 64 bits, 2
banks Double Data Rate (DDR) SDRAM unbuffered
module, mounted 16 pieces of 512M bits DDR SDRAM
sealed in TSOP package. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology. Decoupling capacitors are mounted
beside each TSOP on the module board.
Features
184-pin socket type dual in line memory module
(DIMM)
PCB height: 31.75mm
Lead pitch: 1.27mm
2.5V power supply
Data rate: 333Mbps/266Mbps (max.)
2.5 V (SSTL_2 compatible) I/O
Double Data Rate architecture; two data transfers per
clock cycle
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
Data inputs and outputs are synchronized with DQS
4 internal banks for concurrent operation
(Component)
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
referenced to both edges of DQS
Auto precharge option for each burst access
Programmable burst length: 2, 4, 8
Programmable /CAS latency (CL): 2, 2.5
Refresh cycles: (8192 refresh cycles /64ms)
7.8µs maximum average periodic refresh interval
2 variations of refresh
Auto refresh
Self refresh
Document No. E0296E20 (Ver. 2.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory , Inc. 2002






EBD11UD8ABFB-6B Datasheet, Funktion
EBD11UD8ABFB
Byte No.
28
29
30
31
32
33
34
35
36 to 40
41
42
43
44
45
46 to 61
62
63
Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value
Minimum row active to row active
delay (tRRD)
-6B
0 0 1 1 0 0 0 0 30H
-7A, -7B
0 0 1 1 1 1 0 0 3CH
Minimum /RAS to /CAS delay (tRCD)
-6B
0
1
0
0
1
0
0
0
48H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Minimum active to precharge time
(tRAS)
-6B
0 0 1 0 1 0 1 0 2AH
-7A, -7B
0 0 1 0 1 1 0 1 2DH
Module bank density
1 0 0 0 0 0 0 0 80H
Address and command setup time
before clock (tIS)
-6B
0 1 1 1 0 1 0 1 75H
-7A, -7B
1 0 0 1 0 0 0 0 90H
Address and command hold time after
clock (tIH)
0 1 1 1 0 1 0 1 75H
-6B
-7A, -7B
1 0 0 1 0 0 0 0 90H
Data input setup time before clock
(tDS)
-6B
0 1 0 0 0 1 0 1 45H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Data input hold time after clock (tDH)
-6B
0
1
0
0
0
1
0
1
45H
-7A, -7B
0 1 0 1 0 0 0 0 50H
Superset information
0 0 0 0 0 0 0 0 00H
Active command period (tRC)
-6B
0 0 1 1 1 1 0 0 3CH
-7A, -7B
0 1 0 0 0 1 0 0 44H
Auto refresh to active/
Auto refresh command cycle (tRFC) 0 1 0 0 1 0 0 0 48H
-6B
-7A, -7B
0 1 0 0 1 0 1 1 4BH
SDRAM tCK cycle max. (tCK max.) 0 0 1 1 0 0 0 0 30H
Dout to DQS skew
-6B
0 0 1 0 1 1 0 1 2DH
-7A, -7B
0 0 1 1 0 0 1 0 32H
Data hold skew (tQHS)
-6B
0 1 0 1 0 1 0 1 55H
-7A, -7B
0 1 1 1 0 1 0 1 75H
Superset information
0 0 0 0 0 0 0 0 00H
SPD Revision
Checksum for bytes 0 to 62
-6B
-7A
0 0 0 0 0 0 0 0 00H
0 1 0 0 0 0 1 0 42H
1 1 1 1 1 1 0 0 FCH
-7B 0 0 1 0 0 1 1 1 27H
64 to 65 Manufacturer’s JEDEC ID code
0 1 1 1 1 1 1 1 7FH
Comments
12ns
15ns
18ns
20ns
42ns
45ns
512M bytes
0.75ns*1
0.9ns*1
0.75ns*1
0.9ns*1
0.45ns*1
0.5ns*1
0.45ns*1
0.5ns*1
Future use
60ns*1
68ns*1
75ns*1
75ns*1
12ns*1
450ps*1
500ps*1
550ps*1
750ps*1
Future use
Continuation
code
Preliminary Data Sheet E0296E20 (Ver. 2.0)
6

6 Page









EBD11UD8ABFB-6B pdf, datenblatt
EBD11UD8ABFB
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS = 0V)
(DDR SDRAM Device Specification)
-6B
Parameter
Symbol min.
max.
Clock cycle time
(CL = 2)
tCK 7.5
12
(CL = 2.5)
tCK 6
12
CK high-level width
tCH 0.45
0.55
CK low-level width
tCL 0.45
0.55
CK half period
tHP
DQ output access time from
CK, /CK
tAC
DQS output access time
from CK, /CK
tDQSCK
min
(tCH, tCL)
–0.7
–0.6
0.7
0.6
DQS to DQ skew
tDQSQ —
0.45
DQ/DQS output hold time
from DQS
tQH
tHP – tQHS —
Data hold skew factor
tQHS —
0.55
Data-out high-impedance
time from CK, /CK
Data-out low-impedance
time from CK, /CK
tHZ
tLZ
–0.7
–0.7
0.7
0.7
Read preamble
tRPRE 0.9
1.1
Read postamble
tRPST 0.4
0.6
DQ and DM input setup time tDS
0.45
DQ and DM input hold time tDH
0.45
DQ and DM input pulse
width
tDIPW 1.75
Write preamble setup time tWPRES 0
Write preamble
tWPRE 0.25
Write postamble
tWPST 0.4
0.6
Write command to first DQS
latching transition
tDQSS
DQS falling edge to CK
setup time
tDSS
DQS falling edge hold time
from CK
tDSH
0.75
0.2
0.2
1.25
DQS input high pulse width tDQSH 0.35
DQS input low pulse width tDQSL 0.35
Address and control input
setup time
tIS
Address and control input
hold time
tIH
Address and control input
pulse width
tIPW
Mode register set command
cycle time
tMRD
Active to Precharge
command period
tRAS
Active to Active/Auto refresh
command period
tRC
0.75
0.75
2.2
2
42
60
120000
-7A
min. max
7.5 12
7.5
0.45
0.45
min
(tCH, tCL)
12
0.55
0.55
–0.75
0.75
–0.75
0.75
— 0.5
tHP – tQHS —
— 0.75
–0.75
0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.75
1.1
0.6
0.6
1.25
0.2 —
0.2
0.35
0.35
0.9
0.9 —
2.2 —
2—
45 120000
67.5 —
-7B
min. max
10 12
7.5
0.45
0.45
min
(tCH, tCL)
–0.75
12
0.55
0.55
0.75
–0.75
0.75
— 0.5
tHP – tQHS —
— 0.75
–0.75
0.75
–0.75
0.9
0.4
0.5
0.5
1.75
0
0.25
0.4
0.75
0.75
1.1
0.6
0.6
1.25
0.2 —
0.2
0.35
0.35
0.9
0.9 —
2.2 —
2—
45 120000
67.5 —
Unit Notes
ns 10
ns
tCK
tCK
tCK
ns 2, 11
ns 2, 11
ns 3
ns
ns
ns 5, 11
ns 6, 11
tCK
tCK
ns 8
ns 8
ns 7
ns
tCK
tCK 9
tCK
tCK
tCK
tCK
tCK
ns 8
ns 8
ns 7
tCK
ns
ns
Preliminary Data Sheet E0296E20 (Ver. 2.0)
12

12 Page





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