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E28F400B5B60 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer E28F400B5B60
Beschreibung SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2/ 4/ 8 MBIT
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
E28F400B5B60 Datasheet, Funktion
E
ADVANCE INFORMATION
SMART 5 BOOT BLOCK
FLASH MEMORY FAMILY
2, 4, 8 MBIT
28F200B5, 28F400B5, 28F800B5, 28F004B5
n SmartVoltage Technology
Smart 5 Flash: 5 V Reads,
5 V or 12 V Writes
Increased Programming Throughput
at 12 V VPP
n Very High-Performance Read
2-, 4-Mbit: 60 ns Access Time
8-Mbit: 70 ns Access Time
n x8 or x8/x16-Configurable Data Bus
n Low Power Consumption
Max 60 mA Read Current at 5 V
Auto Power Savings: <1 mA Typical
Standby Current
n Optimized Array Blocking Architecture
16-KB Protected Boot Block
Two 8-KB Parameter Blocks
96-KB and 128-KB Main Blocks
Top or Bottom Boot Locations
n Extended Temperature Operation
–40 °C to +85 °C
n Industry-Standard Packaging
40, 48-Lead TSOP, 44-Lead PSOP
n Extended Block Erase Cycling
100,000 Cycles at Commercial Temp
10,000 Cycles at Extended Temp
n Hardware Data Protection Feature
Absolute Hardware-Protection for
Boot Block
Write Lockout during Power
Transitions
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Reset/Deep Power-Down Input
Provides Low-Power Mode and
Reset for Boot Operations
n Pinout Compatible 2, 4, and 8 Mbit
n ETOX™ Flash Technology
0.6 µ ETOX IV Initial Production
0.4 µ ETOX V Later Production
Intel’s Smart 5 boot block flash memory family provides 2-, 4-, and 8-Mbit memories featuring high-density,
low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Their asymmetrically-
blocked architecture, flexible voltage, and extended cycling provide highly flexible components suitable for
embedded code execution applications, such as networking infrastructure and office automation.
Based on Intel’s boot block architecture, the Smart 5 boot block memory family enables quick and easy
upgrades for designs that demand state-of-the-art technology. This family of products comes in industry-
standard packages: the 40-lead TSOP for very space-constrained 8-bit applications, 48-lead TSOP, ideal for
board-constrained higher-performance 16-bit applications, and the rugged, easy to handle 44-lead PSOP.
December 1997
Order Number: 290599-004






E28F400B5B60 Datasheet, Funktion
SMART 5 BOOT BLOCK MEMORY FAMILY
E
SmartVoltage technology enables fast factory
programming and low-power designs. Specifically
designed for 5 V systems, Smart 5 components
support read operations at 5 V VCC and internally
configure to program/erase at 5 V or 12 V. The 12 V
VPP option renders the fastest program and erase
performance which will increase your factory
throughput. With the 5 V VPP option, VCC and VPP
can be tied together for a simple 5 V design. In
addition, the dedicated VPP pin gives complete data
protection when VPP VPPLK.
The memory array is asymmetrically divided into
blocks in an asymmetrical architecture to
accommodate microprocessors that boot from the
top (denoted by -T suffix) or the bottom (-B suffix)
of the memory map. The blocks include a
hardware-lockable boot block (16,384 bytes), two
parameter blocks (8,192 bytes each) and main
blocks (one block of 98,304 bytes and additional
block(s) of 131,072 bytes). See Figures 4–7 for
memory maps. Each block can be independently
erased and programmed 100,000 times at
commercial temperature or 10,000 times at
extended temperature. Unlike erase operations,
which erase all locations within a block
simultaneously, each byte or word in the flash
memory can be programmed independently of other
memory locations.
The hardware-lockable boot block provides
complete code security for the kernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.3 for details).
The system processor interfaces to the flash device
through a Command User Interface (CUI), using
valid command sequences to initiate device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for program and erase operations. The
Status Register (SR) indicates the status of the
WSM and whether it successfully completed the
desired program or erase operation.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical ICCR current is 1 mA.
When CE# and RP# pins are at VCC, the
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (tPHQV) is
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (tPHEL)
from RP#-high until writes to the CUI are
recognized. See Section 4.2.
The deep power-down mode can also be used as a
device reset, allowing the flash to be reset along
with the rest of the system. For example, when the
flash memory powers-up, it automatically defaults
to the read array mode, but during a warm system
reset, where power continues uninterrupted to the
system components, the flash memory could
remain in a non-read mode, such as erase.
Consequently, the system Reset signal should be
tied to RP# to reset the memory to normal read
mode upon activation of the Reset signal. This also
provides protection against unwanted command
writes due to invalid system bus conditions during
system reset or power-up/down sequences.
These devices are configurable at power-up for
either byte-wide or word-wide input/output using the
BYTE# pin. Please see Table 2 for a detailed
description of BYTE# operations, especially the
usage of the DQ15/A–1 pin.
These Smart 5 memory products are available in
the 44-lead PSOP (Plastic Small Outline Package),
which is ROM/EPROM-compatible, and the 48-lead
TSOP (Thin Small Outline Package, 1.2 mm thick)
as shown in Figure 1, and 2, respectively.
2.0 PRODUCT DESCRIPTION
This section describes the pinout and block
architecture of the device family.
2.1 Pin Descriptions
The pin descriptions table details the usage of each
of the device pins.
6 ADVANCE INFORMATION

6 Page









E28F400B5B60 pdf, datenblatt
SMART 5 BOOT BLOCK MEMORY FAMILY
E
3FFFFH
3C000H
3BFFFH
3A000H
39FFFH
38000H
37FFFH
20000H
1FFFFH
00000H
28F200-T
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
7FFFFH
7C000H
7BFFFH
7A000H
79FFFH
78000H
77FFFH
60000H
5FFFFH
40000H
3FFFFH
20000H
1FFFFH
00000H
28F400-T
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
Byte-Mode Addresses
FFFFFH
FC000H
FBFFFH
FA000H
F9FFFH
F8000H
F7FFFH
E0000H
DFFFFH
C0000H
BFFFFH
A0000H
9FFFFH
80000H
7FFFFH
60000H
5FFFFH
40000H
3FFFFH
20000H
1FFFFH
00000H
28F800-T
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
NOTE: In x8 operation, the least significant system address should be connected to A-1.
Figure 6. Byte-Wide x8-Mode Memory Maps (Top Boot)
0599-05
Byte-Mode Addresses
3FFFFH
20000H
1FFFFH
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
00000H
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
28F200-B
7FFFFH
60000H
5FFFFH
40000H
3FFFFH
20000H
1FFFFH
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
00000H
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
28F400-B
FFFFFH
E0000H
DFFFFH
C0000H
BFFFFH
A0000H
9FFFFH
80000H
7FFFFH
60000H
5FFFFH
40000H
3FFFFH
20000H
1FFFFH
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
00000H
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
96-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
28F800-B
NOTE: In x8 operation, the least significant system address should be connected to A-1.
0599-06
Figure 7. Byte-Wide x8-Mode Memory Maps (Bottom Boot)
12 ADVANCE INFORMATION

12 Page





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