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E28F002BC-T120 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer E28F002BC-T120
Beschreibung 28F002BC 2-MBIT (256K X 8) BOOT BLOCK FLASH MEMORY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
E28F002BC-T120 Datasheet, Funktion
E
PRELIMINARY
28F002BC 2-MBIT (256K X 8)
BOOT BLOCK FLASH MEMORY
n High Performance Read
80/120 ns Max Access Time
40 ns Max. Output Enable Time
n Low Power Consumption
20 mA Typical Read Current
n x8-Only Input/Output Architecture
Space-Constrained 8-bit
Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
One 128-KB Main Block
Top Boot Location
n Hardware Data Protection Feature
Erase/Write Lockout during Power
Transitions
Absolute Hardware Protection for
Boot Block
n Software EEPROM Emulation with
Parameter Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Automated Byte Write and Block Erase
n Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Reset/Deep Power-Down Input
0.2 µA ICC Typical
Provides Reset for Boot Operations
n Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP
40-Lead PDIP
n ETOX™ IV Flash Technology
5V Read
n 12V Write and Block Erase
VPP = 12V ±5% Standard
VPP = 12V ±10% Option
n Independent Software Vendor Support
Intel’s 2-Mbit flash memory is an extension of the Boot Block architecture which includes block-selective
erasure, automated write and erase operations, and a standard microprocessor interface. The 2-Mbit flash
memory enhances the Boot Block architecture by adding more density and blocks, x8 input/output control,
very high-speed, low-power, and industry-standard ROM-compatible pinout and surface mount packaging.
The Intel 28F002BC is an 8-bit wide flash memory offering. This high-density flash memory provides user-
selectable bus operation for 8-bit applications. The 28F002BC is a 2,097,152-bit nonvolatile memory
organized as 262,144 bytes of information. It is offered in 44-lead PSOP, 40- lead PDIP and 40-lead TSOP
package, which is ideal for space-constrained portable systems or any application with board space
limitations.
This device uses an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
byte write and block erasure. The 28F002BC provides block locations compatible with Intel’s MCS®-186
family, 80286, 90860CA, and the Intel386™, Intel486™, Pentium®, and Pentium Pro microprocessors.
The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 80 ns, this high-performance 2-Mbit flash memory interfaces at zero wait-state to a
wide range of microprocessors and microcontrollers. A deep power-down mode lowers the total VCC power
consumption to 1 µW typical. This power savings is critical in hand-held battery powered systems. For very
low-power applications using a 3.3V supply, refer to the Intel 28F002BV-T/B 2-Mbit SmartVoltage Boot Block
Flash Memory datasheet. Manufactured on Intel’s 0.6 micron ETOX™ IV process technology, the 28F002BC
flash memory provides world-class quality, reliability, and cost-effectiveness at the 2-Mbit density.
October 1996
Order Number: 290578-003






E28F002BC-T120 Datasheet, Funktion
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
Pentium®
Processor
100/90 MHz
Host
Bus
Main
Memory
82430FX
PCIset
(82437FX)
Cache
PCI
Bus
ISA
Bus
X-Bus
A[16:0]
82430FX
PCIset
(82371FB)
XX
MM
EE
MM
WR
##
7B
4U
SF
2F
4E
5R
CE#
OE# Intel
28F002BC
WE#
RP#
DQ[7:0]
PWROK
XDIR XOE#
Vpp
J1
0578_01
Figure 1. 28F002BC-T Interface to a Pentium® Microprocessor System
IPP, the maximum program current, is 20 mA. The
VPP voltage for erase and program is 11.4V to
12.6V (VPP = 12V ± 5%) under all operating
conditions. Typical ICC active current is 20 mA.
The 28F002BC flash memory is also designed with
a standby mode to minimize system current drain
and allow for low-power designs. When the CE#
and RP# pins are at VCC, the CMOS standby mode
is enabled and ICC drops to about 50 µA.
A deep power-down mode is enabled when the RP#
pin is at ground. In addition to minimizing power
consumption, the deep power-down mode also
provides write protection during power-up
conditions. ICC current during deep power-down
mode is 0.20 µA typical. An initial maximum access
time or reset time of 300 ns is required from RP#
switching high until outputs are valid. Equivalently,
the device has a maximum wake-up time of 215 ns
until writes to the CUI are recognized.
When RP# is at ground, the WSM is reset, the
status register is cleared, and the entire device is
write-protected. This feature prevents data
corruption and protects the code stored in the
device during system reset. The system Reset pin
can be tied to RP# to reset the memory to read
mode at power-up. With on-chip program/erase
automation and RP# functionality for data
protection, the device is protected against
unwanted program and/or erase cycles, even
during system reset.
1.3 Applications
2-Mbit Boot Block flash memory combines high
density, high performance, and cost-effective flash
memory with blocking and hardware protection
capabilities. Its flexibility and versatility reduces
cost throughout the product life cycle. Flash
memory is ideal for Just-In-Time production flow,
reducing system inventory and costs, and
eliminating component handling during the
production phase. During a product’s life cycle,
flash memory reduces costs by allowing user-
performed code updates and feature enhancements
via floppy disk or remote link.
The 28F002BC is a full-function blocked flash
product suitable for a wide range of applications,
including extended PC BIOS, digital cellular phone
program and data storage, telecommunication
boot/firmware, and various embedded applications
where both program and data storage are required.
6 PRELIMINARY

6 Page









E28F002BC-T120 pdf, datenblatt
28F002BC 2-MBIT BOOT BLOCK FLASH MEMORY
E
2.1 Memory Organization
2.1.1
BLOCKING
The 28F002BC features an asymmetrically-blocked
architecture that provides system memory
integration. Each block can be erased up to
100,000 times. The block sizes have been chosen
to optimize their functionality for common
applications of nonvolatile storage. For the address
locations of the blocks, see the memory map in
Figure 6.
2.1.1.1
Boot Block - 16 KB
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontroller-
based system. The 16-Kbyte (16,384 bytes) boot
block is located at the top of the address map as
shown in Figure 6. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
erasure. The boot block can be erased and written
when RP# is held at 12V for the duration of the
erase or program operation. This feature allows
customers to change the boot code when
necessary while providing security at other times.
3FFFFH
3C000H
3BFFFH
3A000H
39FFFH
38000H
37FFFH
20000H
1FFFFH
00000H
28F002BC-T
16-Kbyte Boot Block
8-Kbyte Parameter Block
8-Kbyte Parameter Block
96-Kbyte Main Block
128-Kbyte Main Block
0578_05
Figure 6. 28F002BC-T Memory Map
12
2.1.1.2
Parameter Blocks - 8 KB (each)
The 28F002BC has two 8-Kbyte parameter blocks
to facilitate storage of frequently updated system
parameters that would normally require an
EEPROM. The parameter blocks can also be used
to store additional boot or main code. By using
software techniques, the byte-rewrite functionality
of EEPROMs can be emulated. These techniques
are detailed in Intel’s application note AP-604 Using
Intel’s Boot Block Flash Memory Parameter Blocks
to Replace EEPROM.
2.1.1.3
Main Block - 96 KB and 128 KB
The 28F002BC contains one 96-Kbyte (98,304
byte) block and one 128-Kbyte (131,072 byte)
block. These blocks are typically used for data or
code storage.
2.1.2
28F002BC-T BLOCK MEMORY MAP
The 16-Kbyte boot block of the 28F002BC-T is
located from 3C000H to 3FFFFH. The first 8-Kbyte
parameter block resides in memory space from
3A000H to 3BFFFH. The second 8-Kbyte
parameter block consumes the memory area from
38000H to 39FFFH. The 96-Kbyte main block
extends from 20000H to 37FFFH, while the
128-Kbyte main block occupies the region from
00000H to 1FFFFH.
3.0 PRINCIPLES OF OPERATION
Flash memory improves upon EPROM capability
with in-circuit electrical write and erase. The Boot
Block flash memory utilizes a Command User
Interface (CUI) and automated algorithms to
simplify write and erase operations. The CUI allows
for 100% TTL-level control inputs, fixed power
supplies during erasure and programming, and
maximum EPROM compatibility.
When VPP < VPPLK, the device will only successfully
execute the following commands: Read Array,
Read Status register, Clear Status register, and
Intelligent Identifier. The device provides standard
EPROM read, standby and output disable
operations. Manufacturer identification and device
identification data can be accessed through the CUI
or through the standard EPROM A9 high voltage
(VID) access for PROM programming equipment.
High voltage on VPP allows write and erase of the
device. With VPP active, all functions associated
PRELIMINARY

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