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E28F001BX-B70 Schematic ( PDF Datasheet ) - Intel Corporation

Teilenummer E28F001BX-B70
Beschreibung 1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY
Hersteller Intel Corporation
Logo Intel Corporation Logo 




Gesamt 30 Seiten
E28F001BX-B70 Datasheet, Funktion
1-MBIT (128K x 8)
BOOT BLOCK FLASH MEMORY
28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B
Y High-Integration Blocked Architecture
One 8 KB Boot Block w Lock Out
Two 4 KB Parameter Blocks
One 112 KB Main Block
Y 100 000 Erase Program Cycles Per
Block
Y Simplified Program and Erase
Automated Algorithms via On-Chip
Write State Machine (WSM)
Y SRAM-Compatible Write Interface
Y Deep Power-Down Mode
0 05 mA ICC Typical
0 8 mA IPP Typical
Y 12 0V g5% VPP
Y High-Performance Read
70 75 ns 90 ns 120 ns 150 ns
Maximum Access Time
5 0V g10% VCC
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Advanced Packaging JEDEC Pinouts
32-Pin PDIP
32-Lead PLCC TSOP
Y ETOXTM II Nonvolatile Flash
Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
Y Extended Temperature Options
Intel’s 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with
features that simplify write and allow block erase These devices aid the system designer by combining the
functions of several components into one making boot block flash an innovative alternative to EPROM and
EEPROM or battery-backed static RAM Many new and existing designs can take advantage of the
28F001BX’s integration of blocked architecture automated electrical reprogramming and standard processor
interface
The 28F001BX-B and 28F001BX-T are 1 048 576 bit nonvolatile memories organized as 131 072 bytes of
8 bits They are offered in 32-pin plastic DIP 32-lead PLCC and 32-lead TSOP packages Pin assignment
conform to JEDEC standards for byte-wide EPROMs These devices use an integrated command port and
state machine for simplified block erasure and byte reprogramming The 28F001BX-T’s block locations pro-
vide compatibility with microprocessors and microcontrollers that boot from high memory such as Intel’s
MCS -186 family 80286 i386TM i486TM i860TM and 80960CA With exactly the same memory segmentation
the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory
such as Intel’s MCS-51 MCS-196 80960KX and 80960SX families All other features are identical and unless
otherwise noted the term 28F001BX can refer to either device throughout the remainder of this document
The boot block section includes a reprogramming write lock out feature to guarantee data integrity It is
designed to contain secure code which will bring up the system minimally and download code to the other
locations of the 28F001BX Intel’s 28F001BX employs advanced CMOS circuitry for systems requiring high-
performance access speeds low power consumption and immunity to noise Its access time provides
no-WAIT-state performance for a wide range of microprocessors and microcontrollers A deep-powerdown
mode lowers power consumption to 0 25 mW typical through VCC crucial in laptop computer handheld instru-
mentation and other low-power applications The RP power control input also provides absolute data protec-
tion during system powerup or power loss
Manufactured on Intel’s ETOX process base the 28F001BX builds on years of EPROM experience to yield the
highest levels of quality reliability and cost-effectiveness
NOTE The 28F001BN is equivalent to the 28F001BX
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290406-007






E28F001BX-B70 Datasheet, Funktion
28F001BX-T 28F001BX-B
PRINCIPLES OF OPERATION
The 28F001BX introduces on-chip write automation
to manage write and erase functions The write state
machine allows for 100% TTL-level control inputs
fixed power supplies during erasure and program-
ming minimal processor overhead with RAM-like
write timings and maximum EPROM compatiblity
After initial device powerup or after return from
deep powerdown mode (see Bus Operations) the
28F001BX functions as a read-only memory Manip-
ulation of external memory-control pins yield stan-
dard EPROM read standby output disable or Intelli-
gent Identifier operations Both Status Register and
Intelligent Identifiers can be accessed through the
Command Register when VPP e VPPL
This same subset of operations is also available
when high voltage is applied to the VPP pin In addi-
tion high voltage on VPP enables successful erasure
and programming of the device All functions associ-
ated with altering memory contents program
erase status and inteligent Identifier are accessed
via the Command Register and verified through the
Status Register
Commands are written using standard microproces-
sor write timings Register contents serve as input to
the WSM which controls the erase and program-
ming circuitry Write cycles also internally latch ad-
dresses and data needed for programming or erase
operations With the appropriate command written to
the register standard microprocessor read timings
output array data access the intelligent identifier
codes or output program and erase status for verifi-
cation
Interface software to initiate and poll progress of in-
ternal program and erase can be stored in any of the
28F001BX blocks This code is copied to and exe-
cuted from system RAM during actual flash memory
update After successful completion of program
and or erase code execution out of the 28F001BX
is again possible via the Read Array command
Erase suspend resume capability allows system
software to suspend block erase and read data exe-
cute code from any other block
Command Register and Write
Automation
An on-chip state machine controls block erase and
byte program freeing the system processor for other
tasks After receiving the erase setup and erase
confirm commands the state machine controls
block pre-conditioning and erase returning progress
via the Status Register Programming is similarly
controlled after destination address and expected
data are supplied The program algorithm of past In-
tel Flash Memories is now regulated by the state
machine including program pulse repetition where
required and internal verification and margining of
data
6
Data Protection
Depending on the application the system designer
may choose to make the VPP power supply switcha-
ble (available only when memory updates are re-
quired) or hardwired to VPPH When VPP e VPPL
memory contents cannot be altered The 28F001BX
Command Register architecture provides protection
from unwanted program or erase operations even
when high voltage is applied to VPP Additionally all
functions are disabled whenever VCC is below the
write lockout voltage VLKO or when RP is at VIL
The 28F001BX accommodates either design prac-
tice and encourages optimization of the processor-
memory interface
The two-step program erase write sequence to the
Command Register provides additional software
write protection
1FFFF
1E000
1DFFF
1D000
1CFFF
1C000
1BFFF
8-KByte BOOT BLOCK
4-KByte PARAMETER BLOCK
4-KByte PARAMETER BLOCK
112-KByte MAIN BLOCK
00000
Figure 7 28F001BX-T Memory Map
1FFFF
112-KByte MAIN BLOCK
04000
03FFF
03000
02FFF
02000
01FFF
4-KByte PARAMETER BLOCK
4-KByte PARAMETER BLOCK
8-KByte BOOT BLOCK
00000
Figure 8 28F001BX-B Memory Map

6 Page









E28F001BX-B70 pdf, datenblatt
28F001BX-T 28F001BX-B
BOOT BLOCK PROGRAM AND
ERASE
The boot block is intended to contain secure code
which will minimally bring up a system and control
programming and erase of other blocks of the de-
vice if needed Therefore additional ‘‘lockout’’ pro-
tection is provided to guarantee data integrity Boot
block program and erase operations are enabled
through high voltage VHH on either RP or OE
and the normal program and erase command se-
quences are used Reference the AC Waveforms for
Program Erase
If boot block program or erase is attempted while
RP is at VIH either the Program Status or Erase
Status bit will be set to ‘‘1’’ reflective of the opera-
tion being attempted and indicating boot block lock
Program erase attempts while VIH k RP k VHH
produce spurious results and should not be attempt-
ed
In-System Operation
For on-board programming the RP pin is the most
convenient means of altering the boot block Before
issuing Program or Erase confirms commands RP
must transition to VHH Hold RP at this high volt-
age throughout the program or erase interval (until
after Status Register confirm of successful comple-
tion) At this time it can return to VIH or VIL
Bus
Operation
Command
Comments
Write
Program
Setup
Data e 40H
Address e Byte to be
Programmed
Write
Program
Data to be programmed
Address e Byte to be
Programmed
Read
Standby
Status Register Data
Toggle OE or CE to
update Status Register
Check SR 7
1 e Ready 0 e Busy
Repeat for subsequent bytes
Full status check can be done after each byte or after a
sequence of bytes
Write FFH after the last byte programming operation to
reset the device to Read Array Mode
Bus
Operation
Command
Comments
Standby
Check SR 3
1 e VPP Low Detect
290406 – 7
Standby
Check SR 4
1 e Byte Program Error
SR 3 MUST be cleared if set during a program attempt
before further attempts are allowed by the Write State
Machine
SR 4 is only cleared by the Clear Status Register
Command in cases where multiple bytes are
programmed before full status is checked
If error is detected clear the Status Register before
attempting retry or other error recovery
Figure 9 28F001BX Byte Programming Flowchart
12

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