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Teilenummer | ADS1245 |
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Beschreibung | Low-Power/ 24-Bit Analog-to-Digital Converter | |
Hersteller | Burr-Brown Corporation | |
Logo | ||
Gesamt 26 Seiten February 2005
ADC12DL040
Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter
General Description
The ADC12DL040 is a dual, low power monolithic CMOS
analog-to-digital converter capable of converting analog in-
put signals into 12-bit digital words at 40 Megasamples per
second (MSPS). This converter uses a differential, pipeline
architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize die size and power con-
sumption while providing excellent dynamic performance
and a 250 MHz Full Power Bandwidth. Operating on a single
+3.0V power supply, the ADC12DL040 achieves 11.1 effec-
tive bits at nyquist and consumes just 210 mW at 40 MSPS,
including the reference current. The Power Down feature
reduces power consumption to 36 mW.
The differential inputs provide a full scale differential input
swing equal to 2 times VREF with the possibility of a single-
ended input. Full use of the differential input is recom-
mended for optimum performance. The digital outputs from
the two ADC’s are available on a single multiplexed 12-bit
bus or on separate buses. Duty cycle stabilization and output
data format are selectable using a quad state function pin.
The output data can be set for offset binary or two’s comple-
ment.
To ease interfacing to lower voltage systems, the digital
output driver power pins of the ADC12DL040 can be con-
nected to a separate supply voltage in the range of 2.4V to
the analog supply voltage.
This device is available in the 64-lead TQFP package and
will operate over the industrial temperature range of −40˚C to
+85˚C. An evaluation board is available to ease the evalua-
tion process.
Features
n Single +3.0V supply operation
n Internal sample-and-hold
n Internal reference
n Outputs 2.4V to 3.6V compatible
n Power down mode
n On-chip reference
n Duty Cycle Stabilizer
n Multiplexed Output Mode
Key Specifications
n Resolution
n DNL
n SNR (fIN = 10 MHz)
n SFDR (fIN = 10 MHz)
n Data Latency
n Power Consumption
n -- Operating
n -- Power Down Mode
Applications
n Ultrasound and Imaging
n Instrumentation
n Communications Receivers
n Sonar/Radar
n xDSL
n Cable Modems
n DSP Front Ends
12 Bits
±0.3 LSB (typ)
69 dB (typ)
85 dB (typ)
7 Clock Cycles
210 mW (typ)
36 mW (typ)
Connection Diagram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation DS201002
20100201
www.national.com
Converter Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR =
+2.5V, PD = 0V, External VREF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On,
parallel output mode. Boldface limits apply for TJ = TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical Limits
(Note 10) (Note 10)
Units
(Limits)
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth
0 dBFS Input, Output at −3 dB
250
MHz
SNR
Signal-to-Noise Ratio
SINAD Signal-to-Noise and Distortion
ENOB Effective Number of Bits
THD
Total Harmonic Distortion
H2 Second Harmonic Distortion
H3 Third Harmonic Distortion
SFDR Spurious Free Dynamic Range
IMD Intermodulation Distortion
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 20 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 20 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 20 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 20 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 20 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 20 MHz, VIN = −0.5 dBFS
fIN = 1 MHz, VIN = −0.5 dBFS
fIN = 10 MHz, VIN = −0.5 dBFS
fIN = 20 MHz, VIN = −0.5 dBFS
fIN = 9.6 MHz and 10.2 MHz,
each = −6.0 dBFS
69
69
68.5
68.5
68.5
68.5
11.1
11.1
11.1
−82
−83
−83
−88
−86
−86.5
−86
−87
−86.5
86
85
84
−75
67.5
67
10.8
-75
-76
-77
76
dB
dB (min)
dB
dB
dB (min)
dB
Bits
Bits (min)
Bits
dB
dB (min)
dB
dB
dB (min)
dB
dB
dB (min)
dB
dB
dB (min)
dB
dBFS
INTER-CHANNEL CHARACTERISTICS
Channel — Channel Offset Match
±0.3
%FS
Channel — Channel Gain Match
±4 %FS
Crosstalk
10 MHz Tested Channel;
20 MHz Other Channel
20 MHz Tested Channel;
10 MHz Other Channel
80
80
dB (min)
dB (min)
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6
6 Page Typical Performance Characteristics DNL, INL Unless otherwise specified, the following
specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +3.0V, VDR = +2.5V, PD = 0V, VREF = +1.0V, fCLK = 40
MHz, fIN = 0, tr = tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On, parallel output mode. Boldface limits apply for TJ =
TMIN to TMAX: all other limits TJ = 25˚C
DNL
INL
DNL vs. fCLK
20100241
INL vs. fCLK
20100245
DNL vs. Clock Duty Cycle
20100242
INL vs. Clock Duty Cycle
20100246
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20100243
12
20100247
12 Page | ||
Seiten | Gesamt 26 Seiten | |
PDF Download | [ ADS1245 Schematic.PDF ] |
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