DataSheet.es    


PDF AV9172-03CC16 Data sheet ( Hoja de datos )

Número de pieza AV9172-03CC16
Descripción Low Skew Output Buffer
Fabricantes Integrated Circuit Systems 
Logotipo Integrated Circuit Systems Logotipo



Hay una vista previa y un enlace de descarga de AV9172-03CC16 (archivo pdf) en la parte inferior de esta página.


Total 8 Páginas

No Preview Available ! AV9172-03CC16 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
AV9172
Low Skew Output Buffer
General Description
The AV9172 is designed to generate low skew clocks for
clock distribution in high-performance PCs and workstations.
It uses phase-locked loop technology to align the phase and
frequency of the output clocks with an input reference clock.
Because the input to output skew is guaranteed to ±500ps, the
part acts as a “zero delay” buffer.
The AV9172 has six configurable outputs. The AV9172-01
version has one output that runs at the same phase and
frequency as the reference clock. A second output runs at the
same frequency as the reference, but can either be in phase or
180° out of phase from the input clock. Two outputs are
provided that are at twice the reference frequency and in
phase with the reference clock. The final outputs can be
programmed to be replicas of the 2x clocks or non-overlapping
two phase clocks at twice the reference frequency. The
AV9172-01 and AV9172-03 operates with input clocks
from 10 MHz to 50 MHz while producing outputs from
10 MHz to 100 MHz. The AV9172-07 operates with input
clocks from 20 to 100 MHz.
The use of a phase-locked loop (PLL) allows the output
clocks to run at multiples of the input clock. This permits
routing of a lower speed clock and local generation of a
required high speed clock. Synchronization of the phase
relationship between the input clock and the output clocks is
accomplished when one output clock is connected to the
input pin FBIN. The PLL circuitry matches rising edges of the
input clock and output clocks.
Block Diagram
Features
• AV9172-07 input is 66 MHz with 66 and 33 MHz
output buffers
• AV9172-01 is pin compatible with Gazelle GA1210E
• ±250ps skew (max) between outputs
• ±500ps skew (max) between input and outputs
• Input frequency range from 10 MHz to 50 MHz
(-01, -03) and from 20 MHz to 100 MHz (-07)
• Output frequency range from 10 MHz to 100 MHz
(-01, -03, -07)
• Special mode for two-phase clock generation
• Inputs and outputs are fully TTL-compatible
• CMOS process results in low power supply current
• High drive, 25mA outputs
• Low cost
• 16-pin SOIC (150-mil) or 16-pin PDIP package
The AV9172 is fabricated using CMOS technology which
results in much lower power consumption and cost compared
with the gallium arsenide-based GA1210E. The typical
operating current for the AV9172 is 50mA versus 120mA for
the GA1210E.
ICS offers several versions of the AV9172. The different
devices are shown below:
PART
AV9172-01
AV9172-03
AV9172-07
DESCRIPTION
Second source of GA1210E
Clock doubler and buffer
Clock buffer for 66 MHz input
AV9172RevB060297P
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.

1 page




AV9172-03CC16 pdf
Pin Configuration
16-Pin SOIC or 16-Pin PDIP
Timing Diagram for AV9172-07
AV9172
Functionality Table for AV9172-07
CLKIN Input Frequency=X, input range is 20 to 100 MHz.
EN2 INV# Q0 Q1 Q2 Q3 Q4 Q5
0 0 1X 1X 1X 1X 1X 1X
1 0 1X 1X 1X 1X 1X 0.5X
0 1 1X 1X 1X 0.5X 0.5X 1X
1 1 1X 1X 1X 0.5X 0.5X 0.5X
Example Table for AV9172-07
(66 MHz input, all frequencies in MHz.)
EN2 INV# Q0 Q1 Q2 Q3 Q4
0 0 66 66 66 66 66
1 0 66 66 66 66 66
0 1 66 66 66 33 33
1 1 66 66 66 33 33
Q5
66
33
66
33
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
5

5 Page










PáginasTotal 8 Páginas
PDF Descargar[ Datasheet AV9172-03CC16.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
AV9172-03CC16Low Skew Output BufferIntegrated Circuit Systems
Integrated Circuit Systems

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar