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PDF AV9107C-13CS08 Data sheet ( Hoja de datos )
| Número de pieza | AV9107C-13CS08 | |
| Descripción | CPU Frequency Generator | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
AV9107C-13
CPU Frequency Generator
General Description
The AV9107C-13 offers a tiny footprint solution for
generating two simultaneous clocks. The AV9107C-13
uses a 20 MHz crystal to generate two PLL synthesis
outputs of 20 and 40 MHz. The Output enable pin will
tristate the 40 MHz output when low (maintaining the 20
MHz output runing in both logic levels). The power pin
takes the device to a low current condition, shutting off the
PLL and forcing both outputs low, when the PD# pin is low.
There is a built-in pull-up on both the OE and PD# inputs.
Features
Patented on-chip Phase-Locked Loop with VCO
for clock generation
Provides two synthesized clocks
Generates 20 and 40 MHz output frequencies.
On-chip loop filter
Low power CMOS technology
Single +3.3 or +5 volt power supply
8-pin SOIC package
The device has advanced features which include on-chip
loop filters, tristate outputs, and power-down capability. A
minimum of external components - two decoupling capacitors
and an optional ferrite bead - are all that are required for jitter-
free operation.
Pin Configuration
Block Diagram
Note: Crystal is 20 MHz
AV 9107-13 RevB052197
1 page  
AV9107C-13
8-Pin Plastic SOIC Package
Ordering Information
AV9107C-13CS08
Example:
XXX XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3 SOIC or .6 DIP; None=StandardWidth
Package Type
S=SOIC
Pattern Number (2 or 3 digit number for parts with ROM code patterns, if applicable)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS,AV=Standard Device; GSP=Genlock Device
5
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| PDF Descargar | [ Datasheet AV9107C-13CS08.PDF ] | |
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