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PDF DF1704 Data sheet ( Hoja de datos )
| Número de pieza | DF1704 | |
| Descripción | Stereo/ 24-Bit/ 96kHz 8X Oversampling Digital Interpolation Filter DIGITAL-TO-ANALOG CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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DF1F70P4O
DF1704
TM Stereo, 24-Bit, 96kHz
8X Oversampling Digital Interpolation Filter
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q COMPANION DIGITAL FILTER FOR THE
PCM1704 24-BIT AUDIO DAC
q HIGH PERFORMANCE FILTER:
Stopband Attenuation: –115dB
Passband Ripple: ±0.00005dB
q AUDIO INTERFACE:
Input Data Formats: Standard, Left-
Justified, and I2S
Input Word Length: 16, 20, or 24 Bits
Output Word Length: 16, 18, 20, or 24 Bits
Sampling Frequency: 32kHz to 96kHz
q SYSTEM CLOCK: 256fS, 384fS, 512fS, 768fS
q ON-CHIP CRYSTAL OSCILLATOR
q PROGRAMMABLE FUNCTIONS:
Hardware or Software Control Modes
Sharp or Slow Roll-Off Filter Response
Soft Mute
Digital De-Emphasis
Independent Left/Right Digital Attenuation
q +5V SINGLE-SUPPLY OPERATION
q SMALL 28-LEAD SSOP PACKAGE
DESCRIPTION
The DF1704 is a high performance, stereo, 8X
oversampling digital interpolation filter designed for
high-end consumer and professional audio applica-
tions. The DF1704 supports 24-bit, 96kHz operation
and features user-programmable functions, including
selectable filter response, de-emphasis, attenuation,
and input/output data formats.
The DF1704 is the ideal companion for Burr-Brown’s
PCM1704 24-bit audio digital-to-analog converter.
This combination allows for construction of very high
performance audio systems and components.
BCKIN
LRCIN
DIN
MD/CKO
MC/LRIP
ML/RESV
MODE
(MUTE)
RST
(DEM)
Serial
Input
I/F
Mode
Control
I/F
8X Oversampling
Digital Filter with
Function
Controller
Output I/F
SCK
Crystal/OSC
Power Supply
BCKO
WCKO
DOL
DOR
(SF0) (SF1) (SRO)
XTI XTO CLKO
VDD
VSS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
PDS-1458B
Printed in U.S.A. December, 1998
1 page  
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER
DE-EMPHASIS (fS = 44.1kHz)
0
–2
–4
–6
–8
–10
0 2 4 6 8 10 12 14 16 18 20
Frequency (fS)
0.01
0.008
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.01
0
DE-EMPHASIS ERROR (fS = 44.1kHz)
2 4 6 8 10 12 14 16 18 20
Frequency (fS)
DE-EMPHASIS (fS = 48kHz)
0
–2
–4
–6
–8
–10
0 2 4 6 8 10 12 14 16 18 20 22
Frequency (fS)
0.01
DE-EMPHASIS ERROR (fS = 48kHz)
0.008
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
–0.008
–0.01
0 2 4 6 8 10 12 14 16 18 20 22
Frequency (fS)
®
5 DF1704
5 Page 
ML(1)
MC(2)
MD
tMCH
tMCL
tMCY
tMDS
tMDH
tMLL
tMHH
tMLH
tMLS
LSB
1.4V
1.4V
1.4V
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Hold Time
MD Set-Up Time
ML Low Level Time
ML High Level Time
ML Hold Time(2)
ML Set-Up Time(3)
tMCY
tMCL
tMCH
tMDH
tMDS
tMLL
tMHH
tMLH
tMLS
100ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns (min)
40ns + 1SYSCLK(3) (min)
40ns + 1SYSCLK(3) (min)
40ns (min)
40ns (min)
NOTES: (1) ML rising edge to the next MC rising edge. (2) MC rising edge for LSB to ML rising edge. (3) SYSCK: System Clock Cycle.
FIGURE 10. Software Interface Timing Requirements.
MODE0 Register
The MODE0 register is used to set the attenuation data for
the Left output channel, or DOL (pin 24).
When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left
channel attenuation data AL[7:0] is used for both the Left
and Right channel attenuators.
When ATC = 0, (Bit B2 of Register MODE3 = 0), Left
channel attenuation data is taken from AL[7:0] of register
MODE0, and Right channel attenuation data is taken from
AR[7:0] of register MODE1.
AL[7:0]
Left Channel Attenuator Data, where AL7 is the
MSB and AL0 is the LSB.
Attenuation Level is given by:
ATTEN = 0.5 • (DATA – 255)dB
For DATA = FFh, ATTEN = –0dB
For DATA = FEh, ATTEN = –0.5dB
For DATA = 01h, ATTEN = –127.5dB
For DATA = 00h, ATTEN = infinity = Mute
LDL Left Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenua-
tion levels of both the Left and Right channels.
When LDL = 1, the Left channel output level is
set by the data in AL[7:0]. The Right channel
output level is set by the data in AL[7:0], or the
most recently programmed data in bits AR[7:0]
of register MODE1.
When LDL = 0, the Left channel output data
remains at its previously programmed level.
MODE1 Register
The MODE1 register is used to set the attenuation data for
the Right output channel, or DOR (pin 23).
When ATC = 1 (Bit B2 of Register MODE3 = 1), the Left
channel attenuation data AL[7:0] of register MODE0 is used
for both the Left and Right channel attenuators.
When ATC = 0, (Bit B2 of Register MODE3 = 0), Left
channel attenuation data is taken from AL[7:0] of register
MODE0, and Right channel attenuation data is taken from
AR[7:0] of register MODE1.
AR[7:0]
Right Channel Attenuator Data, where AR7 is
the MSB and AR0 is the LSB. Attenuation
Level is given by:
ATTEN = 0.5 • (DATA – 255)dB
For DATA = FFh, ATTEN = –0dB
For DATA = FEh, ATTEN = –0.5dB
For DATA = 01h, ATTEN = –127.5dB
For DATA = 00h, ATTEN = infinity = Mute
LDR
Right Channel Attenuation Data Load Control.
This bit is used to simultaneously set attenuation
levels of both the Left and Right channels.
When LDR = 1, the Right channel output level
is set by the data in AR[7:0], or by the data in
bits AL[7:0] of register MODE0. The Left chan-
nel output level is set to the most recently
programmed data in bits AL[7:0] of register
MODE0.
When LDR = 0, the Right channel output data
remains at its previously programmed level.
®
11 DF1704
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DF1704.PDF ] | |
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