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PDF DS92LV18TVV Data sheet ( Hoja de datos )
| Número de pieza | DS92LV18TVV | |
| Descripción | 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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October 2003
DS92LV18
18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz
General Description
The DS92LV18 Serializer/Deserializer (SERDES) pair trans-
parently translates a 18–bit parallel bus into a BLVDS serial
stream with embedded clock information. This single serial
stream simplifies transferring a 18-bit, or less, bus over PCB
traces and cables by eliminating the skew problems between
parallel data and clock paths. It saves system cost by nar-
rowing data paths that in turn reduce PCB layers, cable
width, and connector size and pins.
This SERDES pair includes built-in system and device test
capability. The line loopback feature enables the user to
check the integrity of the serial data transmission paths of
the transmitter and receiver while deserializing the serial
data to parallel data at the receiver outputs. The local loop-
back feature enables the user to check the integrity of the
transceiver from the local parallel-bus side.
The DS92LV18 incorporates modified BLVDS signaling on
the high-speed I/O. BLVDS provides a low power and low
noise environment for reliably transferring data over a serial
transmission path. The equal and opposite currents through
the differential data path control EMI by coupling the result-
ing fringing fields together.
Features
n 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376
Gbps full duplex throughput)
n Independent transmitter and receiver operation with
separate clock, enable, and power down pins
n Hot plug protection (power up high impedance) and
synchronization (receiver locks to random data)
n Wide ±5% reference clock frequency tolerance for easy
system design using locally-generated clocks
n Line and local loopback modes
n Robust BLVDS serial transmission across backplanes
and cables for low EMI
n No external coding required
n Internal PLL, no external PLL components required
n Single +3.3V power supply
n Low power: 90mA (typ) transmitter, 100mA (typ) at 66
MHz with PRBS-15 pattern
n ±100 mV receiver input threshold
n Loss of lock detection and reporting pin
n Industrial −40 to +85˚C temperature range
n >2.0kV HBM ESD
n Compact, standard 80-pin PQFP package
Block Diagram
DS92LV18
© 2003 National Semiconductor Corporation DS200312
20031201
www.national.com
1 page  
Deserializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
HIGH to TRI-STATE
tHZR
Delay
2.2
tLZR
tZHR
LOW to TRI-STATE
Delay
TRI-STATE to HIGH
Delay
Figure 13
ROUT(0-17),
LOCK
2.2
2.3
TRI-STATE to LOW
tZLR
Delay
2.9
tDD
tDSR1
Deserializer Delay
Deserializer PLL
Lock Time from
Powerdown (with
SYNCPAT)
Figure 14,
(Note 7) (Note 8)
RCLK
15MHz
66 MHz
1.75*tRCP + 2.1 1.75*tRCP + 4.0
3.7
1.9
tDSR2
Deserializer PLL
Lock time from
SYNCPAT
Figure 15,
(Note 7) (Note 8)
15MHz
66 MHz
1.5
0.9
Ideal Deserializer
Figure 17
tRNMI-R Noise Margin Right (Note 6) (Note 8)
15 MHz
66 MHz
Ideal Deserializer
tRNMI-L Noise Margin Left
Figure 17
(Note 6) (Note 8)
15 MHz
66 MHz
Total Interconnect
tJI Jitter Budget
(Note 9)
15 MHz
66 MHz
Max
10
10
10
10
1.75*tRCP + 6.1
10
4
5
2
1490
180
1460
330
1060
160
Units
ns
ns
ns
ns
ns
µs
µs
µs
µs
ps
ps
ps
ps
ps
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for VCC = 3.3V and TA = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: tDSR1 is the time required by the deserializer to obtain lock when exiting powerdown mode. tDSR1 is specified with synchronization patterns (SYNCPATs)
present at the LVDS inputs (RI+ and RI-) before exiting powerdown mode. tDSR2 is the time required to obtain lock for the powered-up and enabled deserializer when
the LVDS input (RI+ and RI-) conditions change from not receiving data to receiving synchronization patterns. Both tDSR1 and tDSR2 are specified with the REFCLK
running and stable.
Note 6: tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement
in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: A sync pattern is a fixed pattern with 9-bits of data high followed by 9-bits of data low. The SYNC pattern is automatically generated by the transmitter when
the SYNC pin is pulled high.
Note 8: Guaranteed by Design (GBD) using statistical analysis.
Note 9: Total Interconnect Jitter Budget (tJI) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are DS92LV18 circuits.
tJI is GBD using statistical analysis.
5 www.national.com
5 Page 
AC Timing Diagrams and Test Circuits (Continued)
FIGURE 16. Deterministic Jitter and Ideal Bit Position
20031229
tRNMI-L is the noise margin on the left of the figure above.
tRNMI-R is the noise margin on the right of the above figure.
20031232
FIGURE 17. Deserializer Noise Margin (tRNMI) and Sampling window
11 www.national.com
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