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PDF DS90LV001 Data sheet ( Hoja de datos )
| Número de pieza | DS90LV001 | |
| Descripción | 3.3V LVDS-LVDS Buffer | |
| Fabricantes | National Semiconductor | |
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April 2001
DS90LV001
3.3V LVDS-LVDS Buffer
General Description
The DS90LV001 LVDS-LVDS Buffer takes an LVDS input
signal and provides an LVDS output signal. In many large
systems, signals are distributed across backplanes, and one
of the limiting factors for system speed is the ’stub length’ or
the distance between the transmission line and the untermi-
nated receivers on individual cards. Although it is generally
recognized that this distance should be as short as possible
to maximize system performance, real-world packaging con-
cerns often make it difficult to make the stubs as short as the
designer would like.
The DS90LV001, available in the LLP (Leadless Leadframe
Package) package, will allow the receiver to be placed very
close to the main transmission line, thus improving system
performance.
A wide input dynamic range will allow the DS90LV001 to
receive differential signals from LVPECL as well as LVDS
sources. This will allow the device to also fill the role of an
LVPECL-LVDS translator.
An output enable pin is provided, which allows the user to
place the LVDS output in TRI-STATE.
The DS90LV001 is offered in two package options, an 8 pin
LLP and SOIC.
Features
n Single +3.3 V Supply
n LVDS receiver inputs accept LVPECL signals
n TRI-STATE outputs
n Receiver input threshold < ±100 mV
n Fast propagation delay of 1.4 ns (typ)
n Low jitter 800 Mbps fully differential data path
n 100 ps (typ) of pk-pk jitter with PRBS = 223−1 data
pattern at 800 Mbps
n Compatible with ANSI/TIA/EIA-644-A LVDS standard
n 8 pin SOIC and space saving (70%) LLP package
n Industrial Temperature Range
Connection Diagram
Top View
Block Diagram
DS101338-5
Order Number DS90LV001TM, DS90LV001TLD
See NS Package Number M08A, LDA08A
DS101338-2
© 2001 National Semiconductor Corporation DS101338
www.national.com
1 page  
AC Test Circuits and Timing Diagrams (Continued)
FIGURE 6. TRI-STATE Delay Test Circuit
DS101338-1
DS101338-4
FIGURE 7. Output active to TRI-STATE and TRI-STATE to active output time
5 www.national.com
5 Page 
Typical Performance Curves (Continued)
Differential Propagation Delay vs
Differential Input Voltage
Differential Propagation Delay vs
Common-Mode Voltage
DS101338-31
Peak-to-Peak Output Jitter at VCM = 0.4V vs
Differential Input Voltage
DS101338-32
Peak-to-Peak Output Jitter at VCM = 2.9V vs
Differential Input Voltage
DS101338-33
Peak-to-Peak Output Jitter at VCM = 1.2V vs
Differential Input Voltage
DS101338-35
Peak-to-Peak Output Jitter at VCM = 1.2V vs
Ambient Temperature
DS101338-34
11
DS101338-39
www.national.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet DS90LV001.PDF ] | |
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| DS90LV001TLD | 3.3V LVDS-LVDS Buffer | National Semiconductor |
| DS90LV001TM | 3.3V LVDS-LVDS Buffer | National Semiconductor |
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