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PDF DS90CR485 Data sheet ( Hoja de datos )
| Número de pieza | DS90CR485 | |
| Descripción | 133MHz 48-bit Channel Link Serializer (6.384 Gbps) | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 2003
DS90CR485
133MHz 48-bit Channel Link Serializer (6.384 Gbps)
General Description
The DS90CR485 serializes the 24 LVCMOS/LVTTL double
edge inputs (48 bits data latched in per clock cycle) onto 8
Low Voltage Differential Signaling (LVDS) streams. A phase-
locked transmit clock is also in parallel with the data streams
over a 9th LVDS link. The reduction of the wide TTL bus to a
few LVDS lines reduces cable and connector size and cost.
The double edge input strobes data on both the rising and
falling edges of the clock. This minimizes the pin count
required and simplifies PCB routing between the host chip
and the serializer.
This chip is an ideal solution to solve EMI and interconnect
size problems for high throughput point-to-point applications.
The DS90CR485 is intended for use with the DS90CR486
Channel-Link receiver. It is also backward compatible with
other Channel-Link receiver such as the DS90CR482 and
DS90CR484.
For more details, please refer to the “Applications Informa-
tion” section of this datasheet.
Features
n Up to 6.384 Gbps throughput
n 66MHz to 133MHz input clock support
n Reduces cable and connector size and cost
n Pre-emphasis reduces cable loading effects
n DC balance reduces ISI distortion
n 24 bit double edge inputs
n 3V Tolerant LVCMOS/LVTTL inputs
n Low power, 2.5V supply
n Flow-through pinout
n In 100-pin TQFP package
n Conforms with TIA/EIA-644-A LVDS standard.
Generalized Block Diagram
© 2003 National Semiconductor Corporation DS200195
20019502
www.national.com
1 page  
AC Timing Diagrams (Continued)
FIGURE 5. Setup/Hold with CLKIN
20019553
FIGURE 6. Phase Lock Loop Set Time (VCC ≥ 2.37V)
20019519
FIGURE 7. Power Down Delay
20019521
5 www.national.com
5 Page 
Applications Information
PRE-EMPHASIS
Adds extra current during LVDS logic transition to reduce
cable loading effects. Pre-emphasis strength is set via a DC
voltage level applied from min to max (0.75V to VCC) at the
“PRE” pin. A higher input voltage on the ”PRE” pin increases
the magnitude of dynamic current during data transition. The
“PRE” pin requires one pull-up resistor (Rpre) to VCC in order
to set the DC level. There is an internal resistor network,
which causes a voltage drop. Please refer to Table 1 on
value of Rpre to set the voltage level.
Depending upon interconnect performance and clock rate,
pre-emphasis, DC balance, and deskew enhancements al-
low cables 2 to 7 meters in length to be driven.
TABLE 1. Pre-emphasis with (Rpre)
Rpre
10kΩ or NC
3.5kΩ
1.75KΩ
900Ω
500Ω
50Ω
Effects (Typ)
Standard LVDS
12.5% pre-emphasis
25% pre-emphasis
50% pre-emphasis
75% pre-emphasis
100% pre-emphasis
INFORMATION ON JITTER REJECTION
The transmitter is designed to reject cycle-to-cycle jitter
which may be seen at the transmitter input clock. Very low
cycle-to-cycle jitter is passed on to the transmitter outputs.
Cycle-to-cycle jitter has been measured over frequency to
be less than 100ps with input step function jitter applied. This
significantly reduces the impact of input clock source jitter
and improves the accuracy of data sampling. Transmitter
output jitter is effected by PLLVCC noise and input clock jitter
- minimize supply noise and use a low jitter clock source to
limit output jitter.
DC BALANCE MODE
DC Balance mode is set when the BAL pin on the transmitter
and receiver are tied HIGH - see pin descriptions.
In addition to data information an additional bit is transmitted
on every LVDS data signal line during each cycle as shown
in Figure 10. This bit is the DC balance bit (BAL). The
purpose of the DC Balance bit is to minimize the short- and
long-term DC bias on the signal lines. This is achieved by
selectively sending the data either unmodified or inverted.
The value of the DC balance bit is calculated from the
running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word is
calculated by subtracting the number of bits of value 0 from
the number of bits value 1 in the current word. Initially, the
running word disparity may be any value between +7 and −6.
The running word disparity is the continuous sum of all the
modified data disparity values, where the unmodified data
disparity value is the calculated data disparity minus 1 if the
data is sent unmodified and 1 plus the inverse of the calcu-
lated data disparity if the data is sent inverted. The value of
the running word disparity saturates at +7 and −6 in DC
balance mode. Please refer to Table 2 for DC balance mode
operation.
TABLE 2. DC Balance mode
BAL
0
1
1
1
1
1
Running Word Disparity
X
Positive
Negative
Positive
Negative
Zero
Current Word Disparity
X
Negative/Zero
Positive
Positive
Negative/Zero
X
Data Sent Invert
NO
NO
NO
YES
YES
YES
TSEN
The TSEN pin reports the presence of a remote termination
resistor to the local system. The TSEN pin is an open-
collector output which requires an external pull-up resistor of
1kΩ at 2.5V to function. The logic state output of this pin
determines if there is termination on the far end of the LVDS
clock channel. When TSEN is High, a termination of 100Ω
has been detected. When TSEN is Low, no termination has
been detected indicating the likelihood that the cable is
unplugged. This pin reports the line status to the local sys-
tem.
BIST
To facilitate signal quality testing, an internal test pattern
generator is provided on chip. This can be useful in checking
signal quality (eye patterns) in the link. The internal BIST
function is activated by driving the PRBS_EN pin High.
There are two PRBS patterns available and the selections is
control by the logic state of the PAT_SEL pin. When PAT-
_SEL is High, the transmitter generate and send out a
PRBS-23 pattern. When PAT_SEL is low, a PRBS-15 pattern
will be generated and sent. When PRBS_EN pin is Low, the
logic state of the PAT_SEL pin will be ignored and the
transmitter will operate as indicated by the other control and
input pins. The transmitter’s internally generated PRBS pat-
terns are available for users to monitor signal quality via
eye-diagrams. Depending upon external test equipment re-
quirements, compatibility may or may not be possible.
11 www.national.com
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS90CR485.PDF ] | |
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