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PDF DS90CR483VJD Data sheet ( Hoja de datos )
| Número de pieza | DS90CR483VJD | |
| Descripción | 48-Bit LVDS Channel Link Serializer/Deserializer | |
| Fabricantes | National Semiconductor | |
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February 2000
DS90CR483 / DS90CR484
48-Bit LVDS Channel Link Serializer/Deserializer
General Description
The DS90CR483 transmitter converts 48 bits of CMOS/TTL
data into eight LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a ninth LVDS link. Every
cycle of the transmit clock 48 bits of input data are sampled
and transmitted. The DS90CR484 receiver converts the
LVDS data streams back into 48 bits of CMOS/TTL data. At
a transmit clock frequency of 112MHz, 48 bits of TTL data
are transmitted at a rate of 672Mbps per LVDS data channel.
Using a 112MHz clock, the data throughput is 5.38Gbit/s
(672Mbytes/s).
The multiplexing of data lines provides a substantial cable
reduction. Long distance parallel single-ended buses typi-
cally require a ground wire per active signal (and have very
limited noise rejection capability). Thus, for a 48-bit wide
data and one clock, up to 98 conductors are required. With
this Channel Link chipset as few as 19 conductors (8 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides an 80% reduction in cable width,
which provides a system cost savings, reduces connector
physical size and cost, and reduces shielding requirements
due to the cables’ smaller form factor.
The 48 CMOS/TTL inputs can support a variety of signal
combinations. For example, 6 8-bit words or 5 9-bit (byte +
parity) and 3 controls.
The DS90CR483/DS90CR484 chipset is improved over prior
generations of Channel Link devices and offers higher band-
width support and longer cable drive with three areas of en-
hancement. To increase bandwidth, the maximum clock rate
is increased to 112 MHz and 8 serialized LVDS outputs are
provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. DC
balancing on a cycle-to-cycle basis, is also provided to re-
duce ISI (Inter-Symbol Interference). With pre-emphasis and
DC balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. A cable deskew capability has
been added to deskew long cables of pair-to-pair skew of up
to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These
three enhancements allow cables 5+ meters in length to be
driven.
The chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
For more details, please refer to the “Applications Informa-
tion” section of this datasheet.
Features
n Up to 5.38 Gbits/sec bandwidth
n 33 MHz to 112 MHz input clock support
n LVDS SER/DES reduces cable and connector size
n Pre-emphasis reduces cable loading effects
n DC balance data transmission provided by transmitter
reduces ISI distortion
n Cable Deskew of +/−1 LVDS data bit time (up to 80
MHz Clock Rate)
n 5V Tolerant TxIN and control input pins
n Flow through pinout for easy PCB design
n +3.3V supply voltage
n Transmitter rejects cycle-to-cycle jitter
n Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard
Generalized Block Diagrams
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS100918
DS100918-1
www.national.com
1 page  
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
CLHT
CHLT
RCOP
RCOH
RCOL
RSRC
RHRC
RPDL
RPLLS
RPDD
RSKM
RDR
Parameter
CMOS/TTL Low-to-High Transition Time, (Figure 3),
Rx data out
CMOS/TTL Low-to-High Transition Time, (Figure 3),
Rx clock out
CMOS/TTL High-to-Low Transition Time, (Figure 3),
Rx data out
CMOS/TTL High-to-Low Transition Time, (Figure 3),
Rx clock out
RxCLK OUT Period, (Figure 6)
RxCLK OUT High Time, (Figure
6), (Note 4)
f = 112 MHz
f = 66 MHz
RxCLK OUT Low Time, (Figure 6), f = 112 MHz
(Note 4)
f = 66 MHz
RxOUT Setup to RxCLK OUT,
(Figure 6), (Note 4)
f = 112 MHz
f = 66 MHz
RxOUT Hold to RxCLK OUT,
(Figure 6), (Note 4)
f = 112 MHz
f = 66 MHz
Receiver Propagation Delay - Latency, (Figure 8)
Receiver Phase Lock Loop Set ,(Figure 10)
Receiver Powerdown Delay, (Figure 12)
Receiver Skew Margin without
Deskew, (Figure 13), (Notes 4, 5)
f = 112 MHz
f = 85 MHz
f = 66 MHz
Receiver Deskew Range
f = 80 MHz
RDSS
Receiver Deskew Step Size
f = 80 MHz
Min
8.928
3.5
6.0
3.5
6.0
2.4
3.6
3.4
7.0
3(TCIP)+4.0
170
160
210
± 1.786
(± 1TBIT)
Typ
T
3(TCIP)+4.8
210
200
275
(± 1.3 TBIT)
0.3 TBIT
Max Units
2.0 ns
1.0 ns
2.0 ns
1.0 ns
30.3
3(TCIP)+6.5
10
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
ps
ps
ps
ns
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and T A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except VTH, VTL, VOD and ∆VOD).
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is func-
tionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested to verify functional perfor-
mance.
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPOS). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable) and clock jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle).
5 www.national.com
5 Page 
DS90CR483 Pin Description—Channel Link Transmitter
Pin Name
TxIN
TxOUTP
TxOUTM
TxCLKIN
TxCLKP
I/O No.
Description
I 48 TTL level input. (Note 9).
O 8 Positive LVDS differential data output.
O 8 Negative LVDS differential data output.
I 1 TTL level clock input. The rising edge acts as data strobe.
O 1 Positive LVDS differential clock output.
TxCLKM
PD
PLLSEL
PRE
DS_OPT
VCC
GND
PLLVCC
PLLGND
O 1 Negative LVDS differential clock output.
I 1 TTL level input. Assertion (low input) tri-states the outputs, ensuring low
current at power down. (Note 9).
I 1 PLL range select. This pin must be tied to VCC. NC or tied to Ground is
reserved for future use. (Note 9)
I 1 Pre-emphasis “level” select. Pre-emphasis is active when input is tied to
VCC through external pull-up resistor. Resistor value determines
Pre-emphasis level (See Applications Information Section). For normal
LVDS drive level (No Pre-emphasis) leave this pin open (do not tie to
ground).
I 1 Cable Deskew performed when TTL level input is low. No TxIN data is
sampled during Deskew. To perform Deskew function, input must be held
low for a minimum of 4 clock cycles. The Deskew operation is normally
conducted after the TX and RX PLLs have locked. It should also be
conducted after a system reset, or a reconfiguration event. It must be
peformed at least once when ″DESKEW″ is enabled. (Note 9)
I 8 Power supply pins for TTL inputs and digital circuitry.
I 5 Ground pins for TTL inputs and digital circuitry.
I 2 Power supply pin for PLL circuitry.
I 3 Ground pins for PLL circuitry.
LVDSVCC
LVDSGND
NC
I 3 Power supply pin for LVDS outputs.
I 4 Ground pins for LVDS outputs.
4 No Connect. Make NO Connection to these pins - leave open.
Note 9: Inputs default to “low” when left open due to internal pull-down resistor.
11 www.national.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet DS90CR483VJD.PDF ] | |
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