|
|
PDF DS90CR283MTD Data sheet ( Hoja de datos )
| Número de pieza | DS90CR283MTD | |
| Descripción | 28-Bit Channel Link-66 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS90CR283MTD (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
July 1997
DS90CR283/DS90CR284
28-Bit Channel Link-66 MHz
General Description
The DS90CR283 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR284 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a trans-
mit clock frequency of 66 MHz, 28 bits of TTL data are trans-
mitted at a rate of 462 Mbps per LVDS data channel. Using
a 66 MHz clock, the data throughput is 1.848 Gbit/s
(231 Mbytes/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 28-bit wide
data bus and one clock, up to 58 conductors are required.
With the Channel Link chipset as few as 11 conductors (4
data pairs, 1 clock pair and a minimum of one ground) are
needed. This provides a 80% reduction in required cable
width, which provides a system cost savings, reduces con-
nector physical size and cost, and reduces shielding require-
ments due to the cables’ smaller form factor.
The 28 CMOS/TTL inputs can support a variety of signal
combinations. For example, 7 4-bit nibbles or 3 9-bit (byte +
parity) and 1 control.
Features
n 66 MHz clock support
n Up to 231 Mbytes/s bandwidth
n Low power CMOS design (< 610 mW)
n Power Down mode (< 0.5 mW total)
n Up to 1.848 Gbit/s data throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 56-lead TSSOP package
n Rising edge data strobe
n Compatible with TIA/EIA-644 LVDS Standard
Block Diagrams
DS90CR283
DS90CR284
Order Number DS90CR283MTD
See NS Package Number MTD56
DS012889-27
DS012889-1
Order Number DS90CR284MTD
See NS Package Number MTD56
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS012889
www.national.com
1 page  
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
CLHT
CHLT
RSKM
RCOP
RCOH
RCOL
RSRC
RHRC
RCCD
RPLLS
RPDD
Parameter
CMOS/TTL Low-to-High Transition Time (Figure 3)
CMOS/TTL High-to-Low Transition Time (Figure 3)
RxIN Skew Margin (Note 7),
f = 40 MHz
VCC = 5V, TA = 25˚C (Figure 17)
RxCLK OUT Period (Figure 7)
f = 66 MHz
RxCLK OUT High Time (Figure 7)
f = 40 MHz
f = 66 MHz
RxCLK OUT Low Time (Figure 7)
f = 40 MHz
f = 66 MHz
RxOUT Setup to RxCLK OUT (Figure 7)
f = 40 MHz
f = 66 MHz
RxOUT Hold to RxCLK OUT (Figure 7)
f = 40 MHz
f = 66 MHz
RxCLK IN to RxCLK OUT Delay @ 25˚C,
VCC = 5.0V (Figure 9)
Receiver Phase Lock Loop Set (Figure 11)
Receiver Power Down Delay (Figure 11)
Min Typ Max Units
2.5 4.0
ns
2.0 4.0
ns
700 ps
600 ps
15 T 50
ns
6 ns
4.3 5
ns
10.5
ns
7.0 9
ns
4.5 ns
2.5 4.2
ns
6.5 ns
4 5.2
ns
6.4 10.7 ns
10 ms
1 µs
Note 7: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output skew (TCCS)
and the setup and hold time (internal data sampling window), allowing for LVDS cable skew dependent on type/length and source clock (TxCLK IN) jitter.
RSKM ≥ cable skew (type, length) + source clock jitter (cycle to cycle)
AC Timing Diagrams
FIGURE 1. “WORST CASE” Test Pattern
DS012889-2
DS012889-3
FIGURE 2. DS90CR283 (Transmitter) LVDS Output Load and Transition Timing
DS012889-4
DS012889-5
FIGURE 3. DS90CR284 (Receiver) CMOS/TTL Output Load and Transition Timing
5
DS012889-6
www.national.com
5 Page 
Applications Information (Continued)
plications include flat ribbon, flex, twisted pair and
Twin-Coax. All are available in a variety of configurations and
options. Flat ribbon cable, flex and twisted pair generally per-
form well in short point-to-point applications while Twin-Coax
is good for short and long applications. When using ribbon
cable, it is recommended to place a ground line between
each differential pair to act as a barrier to noise coupling be-
tween adjacent pairs. For Twin-Coax cable applications, it is
recommended to utilize a shield on each cable pair. All ex-
tended point-to-point applications should also employ an
overall shield surrounding all cable pairs regardless of the
cable type. This overall shield results in improved transmis-
sion parameters such as faster attainable speeds, longer
distances between transmitter and receiver and reduced
problems associated with EMS or EMI.
The high-speed transport of LVDS signals has been demon-
strated on several types of cables with excellent results.
However, the best overall performance has been seen when
using Twin-Coax cable. Twin-Coax has very low cable skew
and EMI due to its construction and double shielding. All of
the design considerations discussed here and listed in the
supplemental application notes provide the subsystem com-
munications designer with many useful guidelines. It is rec-
ommended that the designer assess the tradeoffs of each
application thoroughly to arrive at a reliable and economical
cable solution.
BOARD LAYOUT: To obtain the maximum benefit from the
noise and EMI reductions of LVDS, attention should be paid
to the layout of differential lines. Lines of a differential pair
should always be adjacent to eliminate noise interference
from other signals and take full advantage of the noise can-
celing of the differential signals. The board designer should
also try to maintain equal length on signal traces for a given
differential pair. As with any high speed design, the imped-
ance discontinuities should be limited (reduce the numbers
of vias and no 90 degree angles on traces). Any discontinui-
ties which do occur on one signal line should be mirrored in
the other line of the differential pair. Care should be taken to
ensure that the differential trace impedance match the differ-
ential impedance of the selected physical media (this imped-
ance should also match the value of the termination resistor
that is connected across the differential pair at the receiver’s
input). Finally, the location of the CHANNEL LINK TxOUT/
RxIN pins should be as close as possible to the board edge
so as to eliminate excessive pcb runs. All of these consider-
ations will limit reflections and crosstalk which adversely ef-
fect high frequency performance and EMI.
UNUSED INPUTS: All unused inputs at the TxIN inputs of
the transmitter must be tied to ground. All unused outputs at
the RxOUT outputs of the receiver must then be left floating.
TERMINATION: Use of current mode drivers requires a ter-
minating resistor across the receiver inputs. The CHANNEL
LINK chipset will normally require a single 100Ω resistor be-
tween the true and complement lines on each differential
pair of the receiver input. The actual value of the termination
resistor should be selected to match the differential mode
characteristic impedance (90Ω to 120Ω typical) of the cable.
Figure 18 shows an example. No additional pull-up or
pull-down resistors are necessary as with some other differ-
ential technologies such as PECL. Surface mount resistors
are recommended to avoid the additional inductance that ac-
companies leaded resistors. These resistors should be
placed as close as possible to the receiver input pins to re-
duce stubs and effectively terminate the differential lines.
DECOUPLING CAPACITORS: Bypassing capacitors are
needed to reduce the impact of switching noise which could
limit performance. For a conservative approach three
parallel-connected decoupling capacitors (Multi-Layered Ce-
ramic type in surface mount form factor) between each VCC
and the ground plane(s) are recommended. The three ca-
pacitor values are 0.1 µF, 0.01µF and 0.001 µF. An example
is shown in Figure 19. The designer should employ wide
traces for power and ground and ensure each capacitor has
its own via to the ground plane. If board space is limiting the
number of bypass capacitors, the PLL VCC should receive
the most filtering/bypassing. Next would be the LVDS VCC
pins and finally the logic VCC pins.
FIGURE 18. LVDS Serialized Link Termination
DS012889-24
11 www.national.com
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet DS90CR283MTD.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS90CR283MTD | 28-Bit Channel Link-66 MHz | National Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |