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DS5002FP-16 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS5002FP-16
Beschreibung Secure Microprocessor Chip
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 25 Seiten
DS5002FP-16 Datasheet, Funktion
www.maxim-ic.com
GENERAL DESCRIPTION
The DS5002FP secure microprocessor chip is a
secure version of the DS5001FP 128k soft
microprocessor chip. In addition to the memory and
I/O enhancements of the DS5001FP, the secure
microprocessor chip incorporates the most
sophisticated security features available in any
processor. The security features of the DS5002FP
include an array of mechanisms that are designed to
resist all levels of threat, including observation,
analysis, and physical attack. As a result, a massive
effort is required to obtain any information about
memory contents. Furthermore, the “soft” nature of
the DS5002FP allows frequent modification of the
secure information, thereby minimizing the value of
any secure information obtained by such a massive
effort.
PIN CONFIGURATION
TOP VIEW
P0.4AD4
CE2
PE2
BA9
P0.3/AD3
BA8
P0.2/AD2
BA13
P0.1/AD1
R/W
P0.0/AD0
VCC0
VCC
MSEL
P1.0
BA14
P1.1
BA12
P1.2
BA7
P1.3
PE3
PE4
BA6
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1 64
2 63
3 62
4 61
5 60
6
7
Dallas
59
58
8
9
Semiconductor
57
56
10 DS5002FP 55
11 54
12 53
13 52
14 51
15 50
16 49
17 48
18 47
19 46
20 45
21 44
22 43
23 42
24 41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P2.6/A14
CE3
CE4
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
SDI
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
VRST
P3.4/T0
DS5002FP
Secure Microprocessor Chip
FEATURES
§ 8051-Compatible Microprocessor for
Secure/Sensitive Applications
Access 32kB, 64kB, or 128kB of NV SRAM for
Program and/or Data Storage
In-System Programming Through On-Chip Serial
Port
Can Modify Its Own Program or Data Memory in
the End System
§ Firmware Security Features
Memory Stored in Encrypted Form
Encryption Using On-Chip 64-Bit Key
Automatic True Random Key Generator
Self Destruct Input (SDI)
Optional Top Coating Prevents Microprobe
(DS5002FPM)
Improved Security Over Previous Generations
Protects Memory Contents from Piracy
§ Crash-Proof Operation
Maintains All Nonvolatile Resources for Over 10
Years in the Absence of Power
Power-Fail Reset
Early Warning Power-Fail Interrupt
Watchdog Timer
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS5002FP-16
0°C to +70°C
80 QFP
DS5002FPM-16
0°C to +70°C
80 QFP
DS5002FP-16N
-40°C to +85°C 80 QFP
DS5002FMN-16 -40°C to +85°C 80 QFP
Selector Guide appears at end of data sheet.
QFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 030503






DS5002FP-16 Datasheet, Funktion
AC CHARACTERISTICS—POWER CYCLE TIME
(VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 4)
# PARAMETER
32 Slew Rate from VCCMIN to VLI
33 Crystal Startup Time
34 Power-on Reset Delay
SYMBOL
tF
tCSU
tPOR
Figure 4. Power Cycle Timing
DS5002FP Secure Microprocessor Chip
MIN
MAX
UNITS
130 µs
(Note 9)
21504
tCLK
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6 Page









DS5002FP-16 pdf, datenblatt
DS5002FP Secure Microprocessor Chip
PIN NAME
FUNCTION
into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at a logic high when VCC
falls below VLI.
Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It
62 CE4 connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused. CE4
is lithium-backed and remains at a logic high when VCC falls below VLI.
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when the
78
PE1
PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock such as
the DS1283. PE1 is lithium-backed and will remain at a logic high when VCC falls below VLI.
Connect PE1 to battery-backed functions only.
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when the
3 PE2 PES bit is set to a logic 1. PE2 is lithium-backed and will remain at a logic high when VCC falls
below VLI. Connect PE2 to battery-backed functions only.
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when the
22
PE3
PES bit is set to a logic 1. PE3 is not lithium-backed and can be connected to any type of
peripheral function. If connected to a battery-backed chip, it will need additional circuitry to
maintain the chip enable in an inactive state when VCC < VLI.
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when
23
PE4
the PES bit is set to a logic 1. PE4 is not lithium-backed and can be connected to any type of
peripheral function. If connected to a battery-backed chip, it will need additional circuitry to
maintain the chip enable in an inactive state when VCC < VLI.
Invokes the bootstrap loader on a falling edge. This signal should be debounced so that only
32
PROG
one edge is detected. If connected to ground, the micro enters bootstrap loading on power-
up. This signal is pulled up internally.
This I/O pin (open drain with internal pullup) indicates that the power supply (VCC) has fallen
below the VCCMIN level and the micro is in a reset state. When this occurs, the DS5002FP
42
VRST
drives this pin to a logic 0. Because the micro is lithium-backed, this signal is guaranteed
even when VCC = 0V. Because it is an I/O pin, it also forces a reset if pulled low externally.
This allows multiple parts to synchronize their power-down resets.
This output goes to a logic 0 to indicate that the micro has switched to lithium backup. This
43
PF
corresponds to VCC < VLI. Because the micro is lithium-backed, this signal is guaranteed even
when VCC = 0V. The normal application of this signal is to control lithium powered current to
isolate battery-backed functions from non-battery-backed functions.
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the
14
MSEL
DS5002FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5002FP expects to use
a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
Self-Destruct Input. An active high on this pin causes an unlock procedure. This results in the
53 SDI destruction of Vector RAM, Encryption Keys, and the loss of power from VCCO. This pin
should be grounded if not used.
72
CE1N
This is a non-battery-backed version of CE1. It is not generally useful since the DS5002FP
cannot be used with EPROM due to its encryption.
73
N.C.
No Connect
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