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DS4510U-15 Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS4510U-15
Beschreibung CPU Supervisor with Nonvolatile Memory and Programmable I/O
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 12 Seiten
DS4510U-15 Datasheet, Funktion
Rev 2; 8/04
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
General Description
The DS4510 is a CPU supervisor with integrated 64-
byte EEPROM memory and four programmable, non-
volatile (NV) I/O pins. It is configured with an
industry-standard I2C™ interface using either fast-
mode (400kbps) or standard-mode (100kbps) commu-
nication. The I/O pins can be used as general-purpose
I2C-to-parallel I/O expander with unlimited read/write
capability. EEPROM registers allow the power-on value
of the I/O pins to be adjusted to keep track of the sys-
tem’s state through power cycles, and the CPU supervi-
sor’s timer can be adjusted between 125ms and
1000ms to meet most any application need.
Features
Accurate 5%, 10%, or 15% 5V Power-Supply
Monitoring
Programmable Reset Timer Maintains Reset After
VCC Returns to an In-Tolerance Condition
Four Programmable, NV, Digital I/O Pins with
Selectable Internal Pullup Resistor
64 Bytes of User EEPROM
Reduces Need for Discrete Components
I2C-Compatible Serial Interface
10-Pin µSOP Package
Applications
RAM-Based FPGA Bank Switching for
Multiple Profiles
Industrial Controls
Cellular Telephones
PC Peripherals
PDAs
Ordering Information
PART
DS4510U-5
DS4510U-10
DS4510U-15
DS4510U-5/T&R
DS4510U-10/T&R
DS4510U-15/T&R
VCC TRIP
POINT
TEMP RANGE
PIN-
PACKAGE
5% -40°C to +85°C 10 µSOP
10% -40°C to +85°C 10 µSOP
15% -40°C to +85°C 10 µSOP
5% -40°C to +85°C 10 µSOP
10% -40°C to +85°C 10 µSOP
15% -40°C to +85°C 10 µSOP
Pin Configuration
TOP VIEW
A0 1
SDA 2
SCL 3
VCC 4
GND 5
DS4510
µSOP
10 RST
9 I/O0
8 I/O1
7 I/O2
6 I/O3
Typical Operating Circuit
2.7V TO 5.5V
4.7k
FROM
SYSTEM
CONTROLLER
4.7k
A0
SDA
SCL
VCC
DS4510
GND
4.7k
RST RESET VCC
I/O0 CONFIG0
I/O1 CONFIG1 FPGA
I/O2 CONFIG2
I/O3 CONFIG3
GND
I2C is a registered trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc. or one of its
Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
the system conforms to the I2C Standard Specifications as defined by Philips.
______________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.






DS4510U-15 Datasheet, Funktion
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
Functional Diagram
SDA
SCL
2-WIRE
INTERFACE
A0
VCC
VCC
GND
EEPROM
64 BYTES
USER
MEMORY
VCC
DS4510
INTERNAL
VOLTAGE
REFERENCE
PROGRAMMABLE
RESET
TIMER
4x
4 BIDIRECTIONAL
NONVOLATILE I/O LATCHES
PULLUP ENABLE (F0h)
I/OX CONTROL (F4h-F7h)
I/O STATUS (F8h)
VCC
RP
RST
4 NV
I/O PINS
Detailed Description
The DS4510 contains a CPU supervisor, four program-
mable I/O pins, and a 64-byte EEPROM memory. All
functions are configurable or controllable through an
industry-standard I2C-compatible bus. DS4510 NV reg-
isters that are likely to require frequent modification are
implemented using SRAM-shadowed EEPROM (SEEP-
ROM) memory. This memory is configurable to act as
volatile SRAM or NV EEPROM by adjusting the SEE bit
in the Config register. Configuring the SEEPROM as
SRAM eliminates the EEPROM write time and allows
infinite write cycles to these registers. Configuring the
registers as EEPROM allows the application to change
the power-on values that are recalled during power-up.
Programmable CPU Supervisor
The timeout period is adjusted by writing the reset
delay register (SEEPROM). The delay for each setting
is shown in the CPU Supervisor AC Electrical
Characteristics. If the SEE bit is set, changes are writ-
ten to SRAM. On power-up the last value written to the
EEPROM is recalled. The I2C bus is also used to acti-
vate the RST by setting the SWRST bit in the Config
register. This bit automatically returns to zero after the
timeout period. The Config register also contains the
ready, trip point, and reset status bits. The ready bit
determines if the power-on reset level of the DS4510 is
surpassed by VCC. The trip point bit determines if VCC
is above VCCTP, and the reset status bit is set if RST is
in its active state.
Note: The RST pin is an open-drain output, therefore an
external pullup resistor must be used to realize high
logic levels.
Programmable NV Digital I/O Pins
Each programmable I/OX pin contains an input, open-
collector output, and a selectable internal pullup resis-
tor. The DS4510 stores changes to the I/OX pin in
SEEPROM memory. Using the SEEPROM as SRAM is
conducive to applications such as I/O expansion that
generally require fast access times and frequent modi-
fication of the I/OX pin. Configuring the SEEPROM to
behave as EEPROM allows the modification of the
power-on state of the I/OX pin. During power-up the
I/OX pins are high impedance until VCC exceeds 2.0V
(typically), which is when the last value programmed is
recalled from EEPROM. On power-down, the I/OX state
is maintained until VCC drops below 1.9V (typically).
The internal pullups for each I/OX pin are controlled by
the pullup-enable register (F0h). Similarly, the individual
I/OX control registers (F4h to F7h) adjust the pulldown
6 _____________________________________________________________________

6 Page









DS4510U-15 pdf, datenblatt
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
COMMUNICATIONS KEY
S START
A ACK
P STOP
NOT
N ACK
WHITE BOXES INDICATED THE MASTER IS
CONTROLLING SDA
SHADED BOXES INDICATED THE SLAVE IS
CONTROLLING SDA
Sr
REPEATED
START
X X X X X X X X 8-BITS ADDRESS OR DATA
NOTES:
1) ALL BYTES ARE SENT MOST SIGNIFICANT
BIT FIRST.
2) THE FIRST BYTE SENT AFTER A START
CONDITION IS ALWAYS THE SLAVE ADDRESS
FOLLOWED BY THE READ/WRITE BIT.
WRITE A SINGLE BYTE
S 1 0 1 0 0 0 A0 0 A
MEMORY ADDRESS
A
DATA
AP
WRITE UP TO AN 8-BYTE PAGE WITH A SINGLE TRANSACTION
S 1 0 1 0 0 0 A0 0 A MEMORY ADDRESS
A
DATA
A
READ A SINGLE BYTE WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER
S 1 0 1 0 0 0 A0 0 A MEMORY ADDRESS
A Sr 1 0 1 0 0 0 A0 1 A
READ MULTIPLE BYTES WITH A DUMMY WRITE CYCLE TO MOVE THE ADDRESS COUNTER
S 1 0 1 0 0 0 A0 0 A MEMORY ADDRESS
A Sr 1 0 1 0 0 0 A 0 1 A
DATA A P
DATA N P
DATA A
DATA A
DATA A DATA N P
Figure 7. I2C Communications Examples
Chip Topology
TRANSISTOR COUNT: 16559
SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
is a registered trademark of Dallas Semiconductor Corporation.

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