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PDF DS3875 Data sheet ( Hoja de datos )
| Número de pieza | DS3875 | |
| Descripción | Futurebusa Arbitration Controller | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1995
DS3875 Futurebusa Arbitration Controller
General Description
The DS3875 Futurebusa Arbitration Controller is a member
of National Semiconductor’s Futurebusa chip set designed
specifically for the IEEE 896 1 Futurebusa standard The
DS3875 implements Distributed Arbitration and Distributed
Arbitration messages in a single chip
The DS3875 interfaces with Futurebusa through the
DS3885 BTL Arbitration Transceiver and the DS3884A BTL
Handshake Transceiver The DS3885 BTL Arbitration
Transceiver incorporates the competition logic needed for
the Arbitration Number signal lines The DS3884A BTL
Handshake Transceiver has selectable Wired-OR receiver
glitch filtering The DS3884A is used for the Arbitration Se-
quencing and Arbitration Condition signal lines
Additional transceivers included in the Futurebusa chip set
are the DS3883A BTL 9-bit Data Transceiver and the
DS3886A BTL 9-bit Latching Data Transceiver The
DS3886A transceiver features edge-triggered latches in the
driver which may be bypassed during a fall-through mode
and a transparent latch in the receiver The DS3883A trans-
ceiver has no latches in either direction
The Logical Interface Futurebusa Engine (LIFE) I O Proto-
col Controller with 64-bit Data Path incorporates the Com-
pelled Mode Futurebusa Parallel Protocol The Protocol
Controller handles all the handshaking signals between the
Futurebusa and the local bus interfaces and incorporates
a DMA Controller with built-in FIFOs for fast queueing
Features
Y The controller implements the complete requirements
of the IEEE 896 1 specification as a subset of its fea-
tures
Y Supports Arbitration message sending and receiving
Y Supports the two modes of operation (RESTRICTED
UNRESTRICTED)
Y Software configurable double single pass operation
slow fast IBA Parking and restricted unrestricted
modes of arbitration
Y Built-in 1 ms timer for use in the arbitration cycle
Y User programmable 16 arbitration delays (8 slow and
8 fast)
Y Built-in PLL for accurate delays The PLL accepts
clocks from 2 MHz to 40 MHz in steps of 1 MHz
Y Signal to unlock slave modules on transfer of tenure
Auto unlock through a dummy cycle if the current mas-
ter locked resources
Y Programmable delay for releasing ar after issuing
COMPETE IBA CMPT This is to ensure the assertion
of the arbitration number during competition before the
release of ar Also this delay ensures there is suffi-
cient time to assert the AD DATA lines during Idle Bus
Arbitration before the release of ar
Y Read Write facility with data acknowledge for the host
to load arbitration numbers an arbitration message
and control registers
Y On chip parity generator unloads the host of the addi-
tional parity generation function
Y Separate interrupts to indicate error occurrence and ar-
bitration message received Interrupts cleared on a reg-
ister write Error status is available in a separate status
register
Y A special output pin to indicate that a POWERFAIL
message was received
Y Hardwired register to hold the first word of the arbitra-
tion message
Y FIFO strobe provided to store more than one arbitration
message externally to prevent overrun
Y Idle Bus Arbitration (IBA) supported
Y Parking implemented
Y Bus initialization system reset and Live-insertion sup-
ported (The logic to detect these conditions must be
implemented externally )
Y Testability in the form of reading from key registers
which include the STATE MCW 1 ms timer and pro-
grammable input clock divider
National’s Futurebusa Chip Set Diagram
C1995 National Semiconductor Corporation TL H 10747
TL H 10747 – 1
RRD-B30M115 Printed in U S A
1 page  
Pin Definition (Continued)
Pin of Pins Type
Description
SIGNALS TO FROM THE HOST (CPU Plus External Interface Logic)
DATA(7 0)
8 I O Data bus for the host to access the register bank of the controller
ADD(3 0)
4 I Address bits for the register bank of the controller
CS 1 I CHIP SELECT The host can read or write to from the controller
RW
1 I Read write signal from the host
DSACK
1 O Data acknowledge pin for host read write
SEL 1 I SELECT Determines how the controller latches in data A ‘‘1’’ on the pin uses the rising
edge of CS A ‘‘0’’ on the pin uses the falling edge of DSACK
MGRQ
1 I MESSAGE REQUEST Indicates to the controller to send an arbitration message
MGTX
1 O MESSAGE TRANSMIT Indicates the successful transmission of an arbitration message
ERINT
1 O ERROR INTERRUPT Indicates that an error occurred during the arbitration cycle
MGINT
1 O MESSAGE INTERRUPT Indicates the reception of an arbitration message
PFINT
1 O POWER FAIL INTERRUPT Indicates that a powerfail message was received
EXTERNAL LOGIC
IBA CMPT 1 O Signal to indicate that the Parallel Protocol controller may assert its bit on the ADDRESS
DATA bus if it is participating in an Idle Bus Arbitration
IBA S
1 I This signal indicates that IBA was successful If this module was a competitor in the IBA
competition ( BRQ ) then this module is the winner and now the bus master If this module
was the master but did not compete in the IBA competition and IBA was successful then the
M bit (Status register) is negated
AS CANCEL
1
I Indicates the start of the disconnection phase of the current master or cancel the current
arbitration cycle
LKD
1 I LOCKED Signal to indicate that resources have been locked in the current tenure and
hence generate either a dummy cycle if current master or UNLK otherwise (Decoded from
Futurebusa Command port output from Data Path Unit )
UNLK
1 O UNLOCK Transfer of tenure indication to the parallel protocol controller for unlocking its
resources Generated only if the LKD signal is asserted (To external logic )
FSTR
1 O FIFO STROBE Signal generated to load an external FIFO for received arbitration messages
CLK 1 I Clock input to the internal PLL
C1 1 I External capacitor input for PLL 0 1 mF
5
5 Page 
4 0 DS3875 Interfaces (Continued)
FIGURE 3
TL H 10747 – 5
When competing the DS3885 Arbitration Transceiver is en-
abled to place the competition numbers CN(7 0) and its
associated parity bit CNp onto the Futurebusa backplane
During every cycle whether or not competing the winning
module’s arbitration number is read the value of
WIN GT signal and PER signal is determined and up-
dated in the appropriate internal registers
The host can read or write (R W) into the Arbitration Con-
troller registers to change the controller configuration
check status or R W a new arbitration number message
The host can select to latch data either on the falling edge
of DSACK or on the rising edge of CS by releasing or
asserting the SEL pin
The Module may become bus master during Phase 5 if the
normal arbitration cycle was successful Phase 0 if Parking
was successful or Phase 2 if IBA was successful Upon
becoming bus master the Arbitration Controller will issue
BGRNT This signal indicates to the Protocol Controller
that it can now perform the desired transactions on the Par-
allel address data bus
The Protocol Controller will let the Arbitration Controller
know if it has locked resources by asserting the LKD sig-
nal If resources were locked then at transfer of tenure the
Arbitration Controller will issue UNLK to the Protocol Con-
troller to unlock resources
A dummy cycle will be initiated by the Arbitration Controller
to perform the unlocking function if lock (LKD ) is still as-
serted after end of tenure (ENDT ) is asserted and no other
modules are competing Unlock will be asserted at the
transfer of bus tenure (even if this module wins the competi-
tion) If another module initiates arbitration competition this
module will participate in the competition and will issue the
unlock (UNLK ) signal upon transfer of bus tenure When
the bus transaction is complete and no resources are
locked the Protocol Controller has the option of enabling
either Idle Bus Arbitration or parking (IBA PK in CTRL3)
11
11 Page | ||
| Páginas | Total 58 Páginas | |
| PDF Descargar | [ Datasheet DS3875.PDF ] | |
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