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PDF DS3832C-311 Data sheet ( Hoja de datos )

Número de pieza DS3832C-311
Descripción 3.3V/ 32Mb Advanced NV SRAM with Clock
Fabricantes Dallas Semiconducotr 
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DS3832C-311
3.3V, 32Mb Advanced NV SRAM
with Clock
FEATURES
§ 3.0V to 3.6V operation
§ Surface-mount nonvolatile (NV) RAM ball-grid
array (BGA) module construction
§ 1024k x 32 NV SRAM memory space and
separate 64 x 8 real-time clock (RTC)
memory space
§ RTC maintains hundredths of seconds,
seconds, minutes, hours, day, date, month,
and year with leap-year compensation valid
up to 2100
§ Removable backup power source provides
more than eight years of timekeeping and
data retention
§ Read and write access times as fast as 100ns for
NV SRAM memory and 200ns for RTC
§ Automatic data protection during power loss
§ Unlimited write-cycle endurance
§ Low-power CMOS operation
§ Battery monitor checks remaining capacity daily
§ Industrial temperature range of -40°C to
+85°C
PACKAGE OUTLINE
Top View
Bottom View
Side View
Side View
DESCRIPTION
The DS3832C-311 is a 1,048,576 x 32 advanced NV SRAM module with a 168-bump BGA pinout. The
highly integrated DS3832C-311 contains a 64-byte RTC, four 8Mb SRAMs, and control circuitry that
constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the DS3832C-
311 makes use of an attached DS3802 battery cap to maintain clock information and preserve stored data
while protecting that data by disallowing all memory accesses. Additionally, the DS3832C-311 has
dedicated circuitry for monitoring the status of VCC and the status of an attached DS3802 battery cap.
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DS3832C-311 pdf
DS3832C-311
DATA RETENTION MODE
The DS3832C-311 provides full functional capability for VCC greater than 3.0V and write protects by
2.8V. Data is maintained in the absence of VCC without any additional support circuitry. The DS3832C-
311 constantly monitors VCC. Should the supply voltage decay to VTP, the device automatically write
protects itself, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls
below approximately 2.8V, a power-switching circuit electrically connects an attached DS3802 battery
cap to the SRAM to retain data. During power-up, when VCC rises above approximately 2.8V, the power-
switching circuit connects external VCC to the SRAM and disconnects the DS3802 normal RAM
operation can resume after VCC reaches the minimum power-supply voltage.
BATTERY MONITORING
The DS3832C-311 automatically monitors the battery in an attached DS3802 battery cap on a 24-hour
time interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1MW test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the battery cap or DS3802
is replaced. The battery is still retested after each VCC power-up even if BW is active. If the battery
voltage is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open-drain output driver.
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DS3832C-311 arduino
DS3832C-311
AC ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C; VCC= 3.3V ± 0.3V)
NV SRAM
CLOCK
PARAMETER
SYMBOL MIN MAX MIN MAX UNITS NOTES
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
OE or CE to Output
Active
tRC 100
200
ns
tACC 100 200 ns
tOE 50 70 ns
tCO 100 200 ns
tCOE
5
5
ns 6
Output High-Z from
Deselection
tOD
35
50 ns
6
Output Hold from
tOH 5
5
ns
Address Change
Write Cycle Time
tWC 100
200
ns
CE Pulse Width
tCW 100
200
Write Pulse Width
tWP 75
150
ns
Address Setup Time tAW 0 0 ns
Write Recovery Time
tWR1
5
15
ns 12
tWR2
20
20
ns 13
Output High-Z from
tODW
35
50 ns
6
WE
Output Active from
tOEW
5
5
ns 6
WE
Data Setup Time
tDS 40
100
ns 5
Data Hold Time
tDH1
0
0
ns 12
tDH2 20
20
ns 13
TIMING DIAGRAM: READ CYCLE
tRC
ADDRESS
CEX
OEX
DOUT
See Note 2.
tACC
tCO
tOE
tCOE
tCOE
tOH
tOD
tOD
OUTPUT
DATA VALID
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