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DS28E04-100 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS28E04-100
Beschreibung 4096-Bit Addressable 1-Wire EEPROM with PIO
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 30 Seiten
DS28E04-100 Datasheet, Funktion
www.maxim-ic.com
GENERAL DESCRIPTION
The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM
chip with seven address inputs. The address inputs
are directly mapped into the 1-Wire 64-bit Device ID
Number to easily enable the host system to identify
the physical location or functional association of the
DS28E04-100 in a multidevice 1-Wire network en-
vironment. The 4096-bit EEPROM array is configured
as 16 pages of 32 bytes with a 32 byte scratchpad to
perform write operations. EEPROM memory pages
can be individually write protected or put in EPROM-
emulation mode, where bits can only be changed
from a 1 to a 0 state. In addition to the memory, the
DS28E04-100 has two general-purpose I/O ports that
can be used for input or to generate level and/or
pulse outputs. Activity registers also capture port
activity for state change monitoring. The DS28E04-
100 communicates over the single-contact 1-Wire
bus. The communication follows the standard Dallas
Semiconductor 1-Wire protocol.
APPLICATIONS
· Autoconfiguration of Modular Systems such as
Central-Office Switches, Cellular Base Stations,
Access Products, Optical Network Units, and
PBXs
· Accessory/PCB Identification
TYPICAL OPERATING CIRCUIT
VCC
RPUP
PX.Y
µC
LED
IO VCC A6
POL
P1
P0
GND
A0
DS28E04 #1
IO VCC A6
POL
P1
P0
GND
A0
RST1 RST0 DS28E04 #7
DS28E04-100
4096-Bit Addressable 1-Wire EEPROM
with PIO
FEATURES
· 4096 bits of EEPROM Memory Partitioned into
16 Pages of 256 Bits
· Seven Address Inputs for Physical Location
Configuration
· Two General-Purpose PIO Pins with Pulse-
Generation Capability
§ Individual Memory Pages can be Permanently
Write-Protected or put in OTP EPROM-
Emulation Mode (“Write to 0”)
§ Communicates to Host with a Single Digital
Signal at 15.3kbps or 111kbps Using 1-Wire
Protocol
§ Parasitic or VCC Powered
§ Conditional Search Based on PIO Status or PIO
Activity
§ Switchpoint Hysteresis and Filtering to Optimize
Performance in the Presence of Noise
§ Reads and Writes Over a Wide 2.8V to 5.25V
Voltage Range from -40°C to +85°C
§ 16-Pin, 150-mil SO Package
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS28E04S-100
-40°C to +85°C 16 SO (150 mils)
DS28E04S-100/T&R -40°C to +85°C Tape-and-Reel
PIN CONFIGURATION
A3
A2
A1
A0
GND
N.C.
VCC
POL
1 16 IO
2 15 A4
3 14 A5
4 13 A6
5 12 GND
6 11 N.C.
7 10 P1
8 9 P0
SO (150 mils)
Commands, Registers, and Modes are capitalized for
clarity.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS28E04-100 Datasheet, Funktion
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 2. Hierarchical Structure for 1-Wire Protocol
Command
Level:
1-Wire ROM Function
Commands (see Figure 14)
DS28E04-Specific
Memory/Control Function
Commands (see Figure 9)
DS28E04-100
Available
Commands:
Read ROM
Match ROM
Search ROM
Conditional Search
ROM
Skip ROM
Resume
Overdrive Skip
Overdrive Match
Write Scratchpad
Read Scratchpad
Copy Scratchpad
Read Memory
PIO Access Read
PIO Access Write
PIO Access Pulse
Reset Act. Latch
Write Register
Data Field
Affected:
Device ID, RC-Flag
Device ID, RC-Flag
Device ID, RC-Flag
Device ID, RC-Flag, PIO Status,
cond. Search Settings
RC-Flag
RC-Flag
RC-Flag, OD-Flag
Device ID, RC-Flag, OD-Flag
32-byte Scratchpad, Flags
32-byte Scratchpad
Data Memory, Register Page
Data Memory, Registers
PIO Pins
PIO Pins, Activity Latch
PIO Pins, Activity Latch
Activity Latch
Conditional Search and Control
Registers
64-BIT DEVICE ID NUMBER (NETWORK ADDRESS)
Each DS28E04-100 has a unique device ID number that is 64 bits long, as shown in Figure 3. The first 8 bits are a
1-Wire family code. The next 8 bits are an external address byte, of which the lower 7 bits are connected to the
address input pins A0 to A6. This allows the user to set a portion of the Device ID Number by connecting some of
these pins to GND (logic 0) or to VCC (logic 1) or leaving them open (logic 1). The next 40 bits are a lasered serial
number. Even if multiple DS28E04-100 are used in a 1-Wire network and all address inputs are wired to the same
state or left open (unconnected), the unique 40-bit serialization field will prevent any address conflict, allowing to
communicate with each device individually. The last 8 bits are a lasered CRC (Cyclic Redundancy Check) of the
first 56 bits, assuming that the address input pins A0 to A6 are at logic 1. The 1-Wire CRC is generated using a
polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 +
X4 + 1. Further information on the Device ID CRC is found in section CRC Generation near the end of this
document.
Figure 3. 64-Bit Device ID Number
MSB
8-Bit CRC
Code
MSB
LSB
40-Bit Lasered Serial Number
MSB
LSB
LSB
8-Bit External
Address Input
8-Bit Family Code
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
(1Ch)
MSB
LSB MSB
LSB
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DS28E04-100 pdf, datenblatt
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
ADDRESS REGISTERS AND TRANSFER STATUS
The DS28E04-100 employs three address registers, called TA1, TA2, and E/S (Figure 8). Registers TA1 and TA2
must be loaded with the target address to which the data will be written or from which data is read. Register E/S is
a read-only transfer-status register, used to verify data integrity of write commands. The lower five bits of the E/S
register indicate the Ending Offset within the 32-byte scratchpad. Bit 5 of the E/S register, called PF, is set if the
number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due
to a loss of power. A valid write to the scratchpad clears the PF bit. Bit 6 has no function; it always reads 0. Note
that the lowest five bits of the target address also determine the address within the scratchpad, where intermediate
storage of data will begin. This address is called byte offset. If the target address (TA1) for a Write command is
03CH for example, then the scratchpad stores incoming data beginning at the byte offset 1CH and is full after only
four bytes. The corresponding ending offset in this example is 1FH. For maximum data bandwidth, the target
address for writing should point to the beginning of a new page, i.e., the byte offset is 0. Thus the full 32-byte
capacity of the scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write
one or several contiguous bytes somewhere within a page. The ending offset together with the partial flag support
the master checking the data integrity after a Write command. The highest valued bit of the E/S register, called AA
is valid only if the PF flag reads 0. If PF is 0 and AA is 1, a copy has taken place. Writing data to the scratchpad
clears the AA flag.
Figure 8. Address Registers
Bit # 7 6 5 4 3 2 1 0
Target Address (TA1) T7 T6 T5 T4 T3 T2 T1 T0
Target Address (TA2) T15 T14 T13 T12 T11 T10
Ending Address with
Data Status (E/S) AA 0 PF E4 E3 E2
(Read Only)
T9
E1
T8
E0
WRITING WITH VERIFICATION
To write data to the DS28E04-100 EEPROM sections, the scratchpad has to be used as intermediate storage. First
the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be
written to the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an
inverted CRC16 of the command, address (actual address sent), and data (as sent by the master) at the end of the
Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has
calculated to decide whether the communication was successful and proceed to the Copy Scratchpad command. If
the master could not receive the CRC16, it should use the Read Scratchpad command to verify data integrity. As a
preamble to the scratchpad data, the DS28E04-100 repeats the target address TA1 and TA2 and sends the
contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad or there was a loss
of power since data was last written to the scratchpad. The master does not need to continue reading; it can start a
new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the
device did not recognize the Write command. If everything went correctly, both flags are cleared and the ending
offset indicates the address of the last byte written to the scratchpad. Now the master can continue reading and
verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command. This
command must be followed exactly by the data of the three address registers, TA1, TA2, and E/S. The master
should obtain the contents of these registers by reading the scratchpad.
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