Datenblatt-pdf.com


DS2770BE-025 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2770BE-025
Beschreibung Battery Monitor and Charge Controller
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 27 Seiten
DS2770BE-025 Datasheet, Funktion
www.maxim-ic.com
DS2770
Battery Monitor and Charge Controller
FEATURES
§ Integrated charge controller supporting both
rechargeable lithium and NiMH battery
technologies
§ Available in two configurations:
– Internal 25mW current-sense resistor
– External user-selectable sense resistor
§ Current measurement:
– 15-bit bidirectional measurement
– Internal sense resistor configuration:
62.5mA LSB and ±2A dynamic range
– External sense resistor configuration:
1.56mV LSB and ±51.2mV dynamic range
§ Current accumulation
– Internal sense resistor: 0.25mAh LSB
– External sense resistor: 6.25mVh LSB
§ Voltage measurement with 4.88mV resolution
§ Temperature measurement using integrated
sensor with 0.125°C resolution
§ 40 bytes of lockable EEPROM
§ 16 bytes of general-purpose SRAM
§ 42-day timer
§ Dallas 1-Wireâ interface with 64-bit ID
§ 1.8V logic levels
§ Low power consumption:
– Active current: 80mA typical
– Sleep current:
0.5mA typical
PIN ASSIGNMENT
UV
CC
VCH
SNS
SNS
SNS
NC
IS2
1
2
23
4
5
6
7
8
16 VDD
15 VIN
14 DQ
13 VSS
12 VSS
11 VSS
10 NC
9 IS1
DS2770
16-Pin TSSOP
PIN DESCRIPTION
UV – Battery Undervoltage Detect Output
CC – Charge Control Output
VCH – Charge Supply Input
SNS – Sense Resistor Connection
IS2 – Current-Sense Input
IS1 – Current-Sense Input
VSS – Device Ground
DQ – Data Input/Output
VIN – Voltage Sense Input
VDD – Power Supply Input
NC – No Connect
ORDERING INFORMATION
ORDERING NUMBER
MARKING
DS2770AE
D2770EA
DS2770BE
D2770EB
DS2770AE/T&R
D2770EA
DS2770BE/T&R
D2770EB
DS2770AE-025
2770EAR
DS2770BE-025
2770EBR
DS2770AE-025/T&R
2770EAR
DS2770BE-025/T&R
2770EBR
DESCRIPTION
TSSOP, Ext. Sense Res., 4.1V Charge Voltage
TSSOP, Ext. Sense Res., 4.2V Charge Voltage
DS2770AE on Tape & Reel
DS2770BE on Tape & Reel
TSSOP, 25mW Sense Res., 4.1V Charge Voltage
TSSOP, 25mW Sense Res., 4.2V Charge Voltage
DS2770AE-025 on Tape & Reel
DS2770BE-025 on Tape & Reel
1-Wire is a registered trademark of Dallas Semiconductor.
1 of 27
041202






DS2770BE-025 Datasheet, Funktion
DS2770
POWER MODES
The DS2770 has two possible power modes: Active Mode and Sleep Mode. While in Active Mode, the
DS2770 continually measures current, voltage, temperature, and time. Also, current flow is accumulated,
charge control is provided, and data is available to the host system. In Sleep Mode, the DS2770 ceases
these activities. The DS2770 can enter Sleep Mode only when the PMOD bit in the Status Register is set
to 1 and the following other conditions occur:
§ The CINI bit is set to 0 and the DQ line is held low for longer than two seconds. If a charge is in
progress, charging will immediately stop and the device will begin transition to Sleep Mode.
§ The CINI bit is set to 1 and the DQ line is held low for longer than two seconds. If a charge is in
progress, the DS2770 will not go into Sleep Mode until the charge operation is completed.
The DS2770 returns to Active Mode when any of the following occurs:
§ The DQ line is pulled high.
§ The voltage on VCH becomes greater than VDD (charger connection) with the CINI bit set to 1.
Once the DS2770 identifies the 2 second DQ low condition, a transition to Sleep Mode begins. This
process will take up to an additional 11 seconds before the supply current drops to ISLEEP levels.
The DS2770 defaults to Active Mode when power is first applied to VDD.
CHARGER FUNCTION
The DS2770 operates as a standalone charge controller supporting rechargeable lithium and NiMH
battery technologies. The battery type to be charged is selectable through the CTYPE bit of the Status
Register (0 for rechargeable lithium and 1 for NiMH). Charge control of both battery types is performed
by on/off gating of an external constant current or current-limited charge source. If the battery voltage is
less than VLB and a charge source is present, pin UV is driven low, signifying the need to recover the
battery at a reduced rate before fast charging can begin. In Figure 2’s application circuit, UV gates a
trickle-charge current limited by a 360W series resistor. Selection of this resistor depends on the
characteristics of the charge source. UV is driven low independent of any other state of the pack,
including pack temperature and the status of the CINI bit. UV is driven high when the battery voltage
reaches VLB. While trickle charging, a “charge in progress” status is indicated with (0, 1) values,
respectively, in the CSTAT1 and CSTAT0 bits of the Status Register assuming any previous charge
sequence completed status has been cleared.
Fast charging can be initiated by one of two methods:
1) Issuing a Start Charge command [B5h].
2) Introducing a charge supply on the VCH pin when the CINI bit in the Status Register is a 1.
Note that if VDD is below approximately 1.8V prior to using either initiation method, fast charge will not
start after the battery is trickle charged to VLB.
After initiation, the start of fast charge may be postponed if any of the following conditions exist:
§ The temperature is outside the valid charge window specified by TCL (0°C) and TCH (40°C).
§ Charge source is not present (VCH < VDD).
§ Conversion data is not valid (data becomes valid 110ms after waking from Sleep Mode).
§ Battery voltage is less than the low-battery-voltage threshold, VLB, (3.0V).
6 of 27

6 Page









DS2770BE-025 pdf, datenblatt
ELAPSED TIME REGISTER FORMAT Figure 10
DS2770
MSB—Address 02
215 214 213 212 211 210 29 28
MSb
LSb
LSB—Address 03
27 26 25 24 23 22 21 20
MSb
LSb
Units: 0.015625hr
MEMORY
The DS2770 has a 256-byte linear address space with registers for instrumentation, status, and control in
the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining
address space. All EEPROM and SRAM memory is general purpose except addresses 31h, 32h, 33h, and
34h, which should be written with the default values for the Status Register (31h), Current Offset Register
(32h to 33h), and Charge Time Register (34h). When the MSB of any two-byte register is read, both the
MSB and LSB are latched and held for the duration of the Read Data command to prevent updates during
the read and ensure synchronization between two register bytes. For consistent results, always read the
MSB and the LSB of a two-byte register during the same Read Data command sequence.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory actually access shadow RAM. In unlocked EEPROM blocks, the Write Data
command updates shadow RAM. In locked EEPROM blocks, the Write Data command is ignored. The
Copy Data command copies the contents of shadow RAM to EEPROM in an unlocked block of
EEPROM, but has no effect on locked blocks. The Recall Data command copies the contents of a block
of EEPROM to shadow RAM.
Lockable EEPROM is byte programmable and functions as EEPROM until reprogramming is disabled by
the user. The lockable EEPROM can be locked in separate blocks and operate as general EEPROM until
locked by the Lock command [6Axxh]. Reprogramming of the lockable EEPROM blocks is permanently
disabled once the Lock command is used. Addresses 20 to 2Fh comprise a first 16-byte block, addresses
30 to 3Fh comprise a second 16-byte block, and addresses 40 to 47h comprise a third 8-byte block.
Within the second block, address 31h holds the Status Register initialization data, addresses 32h and 33h
hold the Current Offset Register, and address 34h holds the Charge Time Register initialization data. The
Status Register initialization data is supplied to the Status Register in location address 01h on either a
device power up or upon the execution of the Refresh command [63h]. The charge time initialization data
is supplied to the Charge Time Register in address 06h upon the start of fast charge. The Status Register
and the Charge Time Register are both initialized directly from the EEPROM and not from the shadow
RAM. However, the current offset data is supplied directly from the shadow RAM. See the sections on
the Status Register and the Charge Time Register for more detailed information. See the detailed Memory
Map in Figure 11 for more information on the DS2770 memory.
12 of 27

12 Page





SeitenGesamt 27 Seiten
PDF Download[ DS2770BE-025 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
DS2770BE-025Battery Monitor and Charge ControllerDallas Semiconducotr
Dallas Semiconducotr

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche