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DS2740B Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2740B
Beschreibung High-Precision Coulomb Counter
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 15 Seiten
DS2740B Datasheet, Funktion
www.maxim-ic.com
FEATURES
§ 15-Bit Bidirectional Current Measurement
(DS2740)
§ 1.56mV LSB and ±51.2mV Dynamic
Range
§ 78mA LSB and ±2.56A Dynamic
Range with External 20mW Sense
Resistor (RSNS)
§ 156mA LSB and ±5.12A Dynamic
Range with External 10mW Sense
Resistor (RSNS)
§ 13-Bit Bidirectional Current Measurement
(DS2740B)
§ 6.25mV LSB and ±51.2mV Dynamic
Range
§ 312mA LSB and ±2.56A Dynamic
Range with External 20mW Sense
Resistor (RSNS)
§ 625mA LSB and ±5.12A Dynamic
Range with External 10mW Sense
Resistor (RSNS)
§ Analog Input Filter (IS1, IS2) Extends
Dynamic Range for Pulse-Load
Applications
§ Current Accumulation Register
Resolution
§ 6.25mVhr (Both DS2740 and
DS2740B)
§ 0.3125mAhr with External 20mW
RSNS
§ 0.6250mAhr with External 10mW
RSNS
§ Dallas 1-Wire® Interface
§ Unique 64-Bit Device Address
§ Standard and Overdrive Timings
(OVD)
§ Low Power Consumption:
§ Active Current: 65mA max
§ Sleep Current: 1mA max
DS2740
High-Precision Coulomb Counter
PIN CONFIGURATION
OVD 1
8 VDD
PIO 2
7 DQ
SNS
IS2
3
4
6 VSS
5 IS1
mMAX
(DS2740U, DS2740BU)
See Table 1 for Ordering Information.
See Table 2 for Detailed Pin Descriptions.
PIN DESCRIPTION
OVD- 1-Wire Bus Speed Select
PIO - Programmable I/O Pin
SNS - Sense Resistor Input
IS2 - Current-Sense Input
IS1 - Current-Sense Input
VSS - Device Ground, Current-Sense Resistor
Return
DQ - Data Input/Output
VDD - Power-Supply Input (2.7V to 5.5V)
1-Wire is a registered trademark of Dallas Semiconductor.
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DS2740B Datasheet, Funktion
PART
DS2740
DS2740B
VIS1- VIS2
±204.8mVh
ACR RANGE
RSNS
20mW
15mW
10mW
±10.24Ah ±13.65Ah ±20.48Ah
5mW
±40.96Ah
DS2740
MEMORY
The DS2740 has memory space with registers for instrumentation, status, and control. When the MSB of
a two-byte register is read, both the MSB and LSB are latched and held for the duration of the read data
command to prevent updates during the read and ensure synchronization between the two register bytes.
For consistent results, always read the MSB and the LSB of a two-byte register during the same read data
command sequence.
Table 3. MEMORY MAP
ADDRESS (HEX)
DESCRIPTION
00 Reserved
01 Status Register
02 to 07
Reserved
08 Special Feature Register
09 to 0D
Reserved
0E Current Register MSB
0F Current Register LSB
10 Accumulated Current Register MSB
11 Accumulated Current Register LSB
12 to FF
Reserved
READ/WRITE
R
R/W
R
R
R/W
R/W
STATUS REGISTER
The format of the status register is shown in Figure 5. The function of each bit is described in detail in the
following paragraphs.
Figure 5. STATUS REGISTER FORMAT
BIT 7
X
BIT 6
SMOD
ADDRESS 01
BIT 5 BIT 4 BIT 3
X RNAOP X
BIT 2
X
BIT 1
X
BIT 0
X
SMOD—SLEEP Mode Enable. A value of 1 allows the DS2740 to enter sleep mode when DQ is low for
2s. A value of 0 disables DQ related transitions to sleep mode. The power-up default of SMOD = 0.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address
command to 33h, while a 1 sets the opcode to 39h. The power-up default of RNAOP = 0.
X—Reserved bits.
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DS2740B pdf, datenblatt
Table 4. FUNCTION COMMANDS
COMMAND
DESCRIPTION
COMMAND
PROTOCOL
Read Data
Write Data
Reads data from
memory starting at
address XX
Writes data to memory
starting at address XX
69h, XX
6Ch, XX
BUS STATE
AFTER COMMAND
PROTOCOL
Master Rx
Master Tx
DS2740
BUS DATA
Up to 256 bytes
of data
Up to 256 bytes
of data
1-WIRE SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the
DS2740 are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write
1, and read data. All of these types of signaling except the presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2740 is shown in Figure 11.
A presence pulse following a reset pulse indicates that the DS2740 is ready to accept a net address
command. The bus master transmits (Tx) a reset pulse for tRSTL. The bus master then releases the line and
goes into receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After
detecting the rising edge on the DQ pin, the DS2740 waits for tPDH and then transmits the presence pulse
for tPDL.
Figure 11. 1-WIRE INITIALIZATION SEQUENCE
DQ
tRSTL
tPDH
tPDL
tRSTH
LINE TYPE LEGEND:
BUS MASTER ACTIVE LOW
BOTH BUS MASTER AND
DS2740 ACTIVE LOW
DS2740 ACTIVE LOW
RESISTOR PULLUP
PACK+
PACK-
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level
to a logic-low level. There are two types of write-time slots: write 1 and write 0. All write-time slots must
be tSLOT in duration with a 1ms minimum recovery time, tREC, between cycles. The DS2740 samples the
1-Wire bus line between 15ms and 60ms (between 2ms and 6ms for overdrive speed) after the line falls. If
the line is high when sampled, a write 1 occurs. If the line is low when sampled, a write 0 occurs (see
Figure 12). For the bus master to generate a write 1 time slot, the bus line must be pulled low and then
released, allowing the line to be pulled high within 15ms (2ms for overdrive speed) after the start of the
write-time slot. For the host to generate a write 0 time slot, the bus line must be pulled low and held low
for the duration of the write-time slot.
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