|
|
PDF DS2505 Data sheet ( Hoja de datos )
| Número de pieza | DS2505 | |
| Descripción | 16-kbit Add-Only Memory | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de DS2505 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
|
No Preview Available !
www.dalsemi.com
FEATURES
16384 bits Electrically Programmable Read
Only Memory (EPROM) communicates with
the economy of one signal plus ground
Unique, factory-lasered and tested 64-bit
registration number (8-bit family code +
48-bit serial number + 8-bit CRC tester)
assures absolute traceability because no two
parts are alike
Built-in multidrop controller ensures
compatibility with other 1-Wire Net
products
EPROM partitioned into sixty-four 256-bit
pages for randomly accessing packetized data
records
Each memory page can be permanently write-
protected to prevent tampering
Device is an “add only” memory where
additional data can be programmed into
EPROM without disturbing existing data
Architecture allows software to patch data by
superseding an old page in favor of a newly
programmed page
Reduces control, address, data, power, and
programming signals to a single data pin
Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3 kbits per second
8-bit family code specifies DS2505
communications requirements to reader
Presence detector acknowledges when the
reader first applies voltage
Low cost TO-92 or 6-pin TSOC surface
mount package
Reads over a wide voltage range of 2.8V to
6.0V from -40°C to +85°C; programs at
11.5V to 12.0V from -40°C to +50°C
DS2505
16-kbit Add-Only Memory
PIN ASSIGNMENT
TO-92
TSOC PACKAGE
DALLAS
DS2505
GND
DATA
NC
1
2
3
6 NC
5 NC
4 NC
Top View
3.7 X 4.0 X 1.5 mm
Side View
See Mech.
Drawing Section
12 3
Bottom View
See Mech.
Drawings Section
ORDERING INFORMATION
DS2505
TO-92 Package
DS2505P
6-pin TSOC Package
DS2505/T&R Tape & Reel version of DS2505
DS2505P/T&R Tape & Reel version of DS2505P
1 of 24
032201
1 page  
DS2505
EPROM STATUS BYTES
In addition to the 16384 bits of data memory the DS2505 provides 704 bits of Status Memory accessible
with separate commands.
The EPROM Status Bytes can be read or programmed to indicate various conditions to the software
interrogating the DS2505. The first 8 bytes of the EPROM Status Memory (addresses 000 to 007H)
contain the Write Protect Page bits which inhibit programming of the corresponding page in the 16384-bit
main memory area if the appropriate write protection bit is programmed. Once a bit has been
programmed in the Write Protect Page section of the Status Memory, the entire 32-byte page that
corresponds to that bit can no longer be altered but may still be read.
The next 8 bytes of the EPROM Status Memory (addresses 020 to 027H) contain the Write Protect bits
which inhibit altering the Page Address Redirection Byte corresponding to each page in the 16384-bit
main memory area.
The following 8 bytes within the EPROM Status Memory (addresses 040 to 047H) are reserved for use
by the iButton operating software TMEX. Their purpose is to indicate which memory pages are already
in use. Originally, all of these bits are unprogrammed, indicating that the device does not store any data.
As soon as data is written to any page of the device under control of TMEX, the bit inside this bitmap
corresponding to that page will be programmed to 0, marking this page as used. These bits are
application flags only and have no impact on the internal logic of the DS2505.
The next 64 bytes of the EPROM Status Memory (addresses 100H to 13FH) contain the Page Address
Redirection Bytes which indicate if one or more of the pages of data in the 16384-bit EPROM section
have been invalidated by software and redirected to the page address contained in the appropriate
redirection byte. The hardware of the DS2505 makes no decisions based on the contents of the Page
Address Redirection Bytes. These additional bytes of Status EPROM allow for the redirection of an
entire page to another page address, indicating that the data in the original page is no longer considered
relevant or valid. With EPROM technology, bits within a page can be changed from a logical 1 to a
logical 0 by programming, but cannot be changed back. Therefore, it is not possible to simply rewrite a
page if the data requires changing or updating, but with space permitting, an entire page of data can be
redirected to another page within the DS2505 by writing the one’s complement of the new page address
into the Page Address Redirection Byte that corresponds to the original (replaced) page.
This architecture allows the user’s software to make a “data patch” to the EPROM by indicating that a
particular page or pages should be replaced with those indicated in the Page Address Redirection Bytes.
To leave an authentic audit trail of data patches, it is recommended to also program the write protect bit
of the Page Address Redirection Byte, after the page redirection is programmed. Without this protection,
it is still possible to modify the Page Address Redirection Byte, making it point to a different memory
page than the true one.
If a Page Address Redirection Byte has a FFH value, the data in the main memory that corresponds to
that page is valid. If a Page Address Redirection Byte has some other hex value, the data in the page
corresponding to that redirection byte is invalid, and the valid data can now be found at the one’s
complement of the page address indicated by the hex value stored in the associated Page Address
Redirection Byte. A value of FDH in the redirection byte for page 1, for example, would indicate that the
updated data is now in page 2. The details for reading and programming the EPROM status memory
portion of the DS2505 are given in the Memory Function Commands section.
5 of 24
5 Page 
DS2505
Note that the initial pass through the Read Status flow chart will generate a 16-bit CRC value that is the
result of clearing the CRC generator and then shifting in the command byte followed by the 2 address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing through
to the last byte of the addressed EPROM Status data page. The last byte of a Status data page always has
an ending address of xx7 or xxFH. Subsequent passes through the Read Status flow chart will generate a
16-bit CRC that is the result of clearing the CRC generator and then shifting in the new data bytes,
starting at the first byte of the next page of the EPROM Status data field.
This feature is provided since the EPROM Status information may change over time, making it
impossible to program the data once and include an accompanying CRC that will always be valid.
Therefore, the Read Status command supplies a 16-bit CRC that is based on and always is consistent with
the current data stored in the EPROM Status data field. After the 16-bit CRC of the last EPROM Status
data page is read, the bus master will receive logical 1s from the DS2505 until a reset pulse is issued. The
Read Status command sequence can be ended at any point by issuing a reset pulse.
EXTENDED READ MEMORY [A5H]
The Extended Read Memory command supports page redirection when reading data from the 16384-bit
EPROM data field. One major difference between the Extended Read Memory and the basic Read
Memory command is that the bus master receives the Redirection Byte first before investing time in
reading data from the addressed memory location. This allows the bus master to quickly decide whether
to continue and access the data at the selected starting page or to terminate and restart the reading process
at the redirected page address. A non-redirected page is identified by a Redirection Byte with a value of
FFH (see description of EPROM Status Bytes). If the Redirection Byte is different than this, the master
has to complement it to obtain the new page number. Multiplying the page number by 32 (20H) results in
the new address the master has to send to the DS2505 to read the updated data replacing the old data.
There is no logical limitation in the number of redirections of any page. The only limit is the number of
available memory pages within the DS2505.
In addition to page redirection, the Extended Read Memory command also supports “bit-oriented”
applications where the user cannot store a 16-bit CRC with the data itself. With bit-oriented applications
the EPROM information may change over time within a page boundary, making it impossible to include
an accompanying CRC that will always be valid. Therefore, the Extended Read Memory command
concludes each page with the DS2505 generating and supplying a 16-bit CRC that is based on and
therefore always consistent with the current data stored in each page of the 16384-bit EPROM data field.
After having sent the command code of the Extended Read Memory command, the bus master follows
the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte
location within the data field. By sending eight read data time slots, the master receives the Redirection
Byte associated with the page given by the starting address. With the next 16 read data time slots, the bus
master receives a 16-bit CRC of the command byte, address bytes and the Redirection Byte. This CRC is
computed by the DS2505 and read back by the bus master to check if the command word, starting address
and Redirection Byte were received correctly.
If the CRC read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must
be repeated. If the CRC received by the bus master is correct, the bus master issues read time slots and
receives data from the DS2505 starting at the initial address and continuing until the end of a 32-byte
page is reached. At that point the bus master will send 16 additional read time slots and receive a 16-bit
CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte
to the last byte of the current page.
11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet DS2505.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS2501 | 1A VERY LOW DROPOUT VOLTAGE REGULATORS |  Advanced Monolithic Systems |
| DS2501 | (DS2501 / DS2502) Add Only Memory |  Dallas Semiconductor |
| DS2502 | 1 kbit Add-Only Memory | Dallas Semiconducotr |
| DS2502 | DS2502 | Dallas Semiconducotr |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |