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DS2450 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2450
Beschreibung 1-Wire Quad A/D Converter
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 24 Seiten
DS2450 Datasheet, Funktion
www.dalsemi.com
DS2450
1-WireTM Quad A/D Converter
FEATURES
§ Four high-impedance inputs to measure
analog voltages over the 1-Wire bus
§ User programmable input range (2.56V,
5.12V), resolution (1 to 16 bits) and alarm
thresholds
§ 5V, single supply operation
§ Very low power: 2.5 mW active, 25 µW idle
§ Built-in multidrop controller allows multiple
DS2450’s to be identified and operated on a
common 1-Wire bus
§ Responds to Conditional Search if the analog
voltage crosses the alarm thresholds
§ Channels not used as analog input can serve
as open drain digital outputs for closed-loop
control
§ Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3k bits per second
§ Overdrive mode boosts communication speed
to 142k bits per second
§ On-chip 16-bit CRC-generator for
safeguarding data transfers
§ Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number 8-bit CRC tester) assures
absolute traceability because no two parts are
alike
§ 8-bit family code specifies device
communication requirements to bus master
§ Operating temperature range from -40°C to
+85°C
§ Compact, low cost 8-pin SOIC surface mount
package
PIN ASSIGNMENT
VCC 1 8 AIN-D
NC 2 7 AIN-C
DATA 3 6 AIN-B
GND 4 5 AIN-A
8-PIN SOIC (208 MIL)
PIN DESCRIPTION
VCC 4.5 to 5.5 Volts
NC Do Not Connect
DATA
1-Wire Bus
GND
Ground
AIN-A
Analog Input A
AIN-B
Analog Input B
AIN-C
Analog Input C
AIN-D
Analog Input D
ORDERING INFORMATION
DS2450S
8-pin SOIC
DESCRIPTION
The DS2450 1-Wire Quad A/D Converter is based on a successive-approximation analog to digital
converter with a four to one analog multiplexer. Each input channel has its own register set to store the
input voltage range, resolution, and alarm threshold values as well as flags to enable participation of the
device in the conditional search if the input voltage leaves the specified range. Two alarm flags for each
channel indicate if the voltage measured was too high or too low without requiring the bus master to do
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DS2450 Datasheet, Funktion
MEMORY MAP PAGE 2, ALARM SETTINGS Figure 5c
Address bit 7
bit 6
bit 5
bit 4
bit 3
10 MSBL-A A A A A
11 MSBH-A
A
A
A
A
12 MSBL-B B B B B
13 MSBH-B B B B B
14 MSBL-C C C C C
15 MSBH-C C C C C
16 MSBL-D
D
D
D
D
17 MSBH-D D D D D
bit 2
A
A
B
B
C
C
D
D
DS2450
bit 1
A
A
B
B
C
C
D
D
bit 0
LSBL-A
LSBH-A
LSBL-B
LSBH-B
LSBL-C
LSBH-C
LSBL-D
LSBH-D
The registers for the alarm threshold voltages of each channel are located in memory page 2 with the low
threshold being at the lower address (Figure 5c). The power-on default thresholds are 00h for low alarm
and FFh for high alarm. The alarm settings are always eight bits. For a resolution higher or equal to
eight bits the alarm flag will be set if the eight most significant bits of the conversion result yield a
number higher than stored in the high alarm register (AFH) or lower than stored in the low alarm register
(AFL). For a resolution lower than eight bits the least significant bits of the alarm registers are ignored.
There is a fourth memory page in the address range of 18 to 1F used during calibration at the factory.
This memory page is accessible to the user through the Read Memory and Write Memory commands.
Changing the data of this page arbitrarily will de-calibrate the A/D converter or make the device
nonfunctional until it undergoes a power-on reset. If the device is VCC powered the analog circuitry
must be kept permanently active by writing a value of 40 hex to memory address 1C after power-up.
This also eliminates the offset time otherwise needed with each CONVERT command. See the
description of the CONVERT command for details.
FUNCTION COMMANDS
The Function Command Flow Chart (Figure 6) describes the protocols necessary for accessing the device
registers. Since the memory map of the DS2450 is small compared to the 16-bit addressing capabilities
the 11 most significant bits of the address will be forced to 0 before they enter the CRC-generator. The
communication between master and DS2450 takes place either at regular speed (default, OD = 0) or at
Overdrive Speed (OD = 1). If not explicitly set into Overdrive mode the device assumes regular speed.
READ MEMORY [AAH]
The Read Memory command is used to read conversion results, control/status data and alarm settings.
The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that
indicates a starting byte location within the memory map. With every subsequent read data time slot the
bus master receives data from the DS2450 starting at the supplied address and continuing until the end of
an eight-byte page is reached. At that point the bus master will receive a 16-bit CRC of the command
byte, address bytes and data bytes. This CRC is computed by the DS2450 and read back by the bus
master to check if the command word, starting address and data were received correctly. If the CRC read
by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated.
Note that the initial pass through the Read Memory flow chart will generate a 16-bit CRC value that is the
result of clearing the CRC-generator and then shifting in the command byte followed by the two address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing through
to the last byte of the addressed page. Subsequent passes through the Read Memory flow chart will
generate a 16-bit CRC that is the result of clearing the CRC-generator and then shifting in the new data
bytes starting at the first byte of the next page.
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DS2450 pdf, datenblatt
TRANSACTION SEQUENCE
The protocol for accessing the DS2450 via the 1-Wire port is as follows:
§ Initialization
§ ROM Function Command
§ Memory/Convert Function Command
§ Transaction/Data
DS2450
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2450 is on the bus and is ready to
operate. For more details, see the “1-Wire Signaling” section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the seven ROM function commands. All
ROM function commands are eight bits long. A list of these commands follows (refer to flowchart in
Figure 9):
Read ROM [33H]
This command allows the bus master to read the DS2450’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used if there is a single DS2450 on the bus. If more
than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same
time (open drain will produce a wired-AND result). The resultant family code and 48-bit serial number
will result in a mismatch of the CRC.
MATCH ROM [55H]
The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a
specific DS2450 on a multidrop bus. Only the DS2450 that exactly matches the 64-bit ROM sequence
will respond to the following memory/convert function command. All slaves that do not match the 64-bit
ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices
on the bus.
SKIP ROM [CCH]
This command can save time in a single drop bus system by allowing the bus master to access the
memory/ convert functions without providing the 64-bit ROM code. If more than one slave is present on
the bus and a read command is issued following the Skip ROM command, data collision will occur on the
bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired-AND result).
SEARCH ROM [F0H]
When a system is initially brought up, the bus master might not know the number of devices on the 1-
Wire bus or their 64-bit ROM codes. The Search ROM command allows the bus master to use a process
of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process
is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the
desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM.
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Chapter 5 of the
Book of DS19xx iButton Standards for a comprehensive discussion of a Search ROM, including an actual
example.
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