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PDF DS2432 Data sheet ( Hoja de datos )
| Número de pieza | DS2432 | |
| Descripción | 1k-Bit Protected 1-Wire EEPROM with SHA-1 Engine | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de DS2432 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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www.dalsemi.com
Preliminary
DS2432
1k-Bit Protected 1-Wire™
EEPROM with SHA-1 Engine
FEATURES
1128 bits of 5V EEPROM memory parti-
tioned into four pages of 256 bits, a 64-bit
write-only secret and up to 5 general purpose
read/write registers
On-chip 512-bit SHA-1 engine to compute
160-bit Message Authentication Codes
(MAC) and to generate secrets
Write access requires knowledge of the secret
and the capability of computing and transmit-
ting a 160-bit MAC as authorization
Secret and data memory can be write-pro-
tected (all or page 0 only) or put in EPROM-
emulation mode (“write to 0”, page 1)
Unique, factory-lasered and tested 64-bit reg-
istration number assures absolute traceability
because no two parts are alike
Built-in multidrop controller ensures compati-
bility with other 1-Wire net products
Reduces control, address, data and power to a
single data pin
Directly connects to a single port pin of a mi-
croprocessor and communicates at up to 16.3k
bits per second
Overdrive mode boosts communication speed
to 142k bits per second
Low cost 6-lead TSOC surface mount pack-
age, or solder-bumped Flipchip package
Reads and writes over a wide voltage range of
2.8V to 5.25V from -40°C to +85°C
PIN ASSIGNMENT
TSOC (150mil)
GND 1
1-WIRE 2
NC 3
6 NC
5 NC
4 NC
top view
side view
top view
See www.dalsemi.com for mechanical
specifications of packages.
ORDERING INFORMATION
DS2432P
6-lead TSOC package
DS2432P/T&R Tape & Reel DS2432P
DS2432X
Flipchip package, tape & reel
DESCRIPTION
The DS2432 combines 1024 bits of EEPROM, a 64-bit secret, an 8-byte register/control page with up to 5
user read/write bytes, a 512-bit SHA-1 engine and a fully-featured 1-Wire interface in a single chip. Each
DS2432 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a
guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol,
which requires only a single data lead and a ground return. The DS2432 has an additional memory area
called the scratchpad that acts as a buffer when writing to the main memory, the register page or when
installing a new secret. Data is first written to the scratchpad from where it can be read back. After the
data has been verified, a copy scratchpad command will transfer the data to its final memory location,
provided that the DS2432 receives a matching 160-Bit MAC. The computation of the MAC involves the
secret and additional data stored in the DS2432 including the device’s registration number. Only a new
secret can be loaded without providing a MAC. The SHA-1 engine can also be activated to compute
1 of 30
040201
1 page  
PRELIMINARY
DS2432
The secret can be installed either by copying data from the scratchpad to the secrets memory or by
computation using the current secret and the scratchpad contents as partial secret. The secret cannot be
read directly; only the SHA engine has access to it for computing message authentication codes.
The address range 0088h to 008Fh, also referred to as register page, contains special function registers as
well as general-purpose user-bytes and one factory byte. Once programmed to AAh or 55h, most of these
bytes become write-protected and can no longer be altered. All other codes will neither write-protect the
address nor activate the special function associated to that particular byte. Special functions are: 1) write-
protecting only the secret, 2) write-protecting all four data memory pages simultaneously, 3) activating
EPROM mode for data memory page 1 only, and 4) write-protecting data memory page 0 only. Once the
EPROM mode is activated, bits in the address range 0020h through 003Fh can only be altered from a
logic 1 to a logic 0, provided that the data memory is not write protected.
The factory byte will either read 55H or AAh. Typically, this address will read 55h, indicating that the
addresses 008E and 008F are read/write user-bytes without any special function or locking mechanism.
The code of AAh indicates that these two bytes are programmed with a 16-bit manufacturer ID and then
write-protected at the factory. The manufacturer ID can be a customer-supplied identification code that
assists the application software in identifying the product the DS2432 is associated with and in faster
selection of the applicable secret. To setup and register a manufacturer ID contact the factory.
The address range 0090h to 0097h provides an alternate way to read the device’s ROM registration
number. The family code is stored at the lower address followed by the 48-bit serial number and the 8-bit
CRC, which is stored at address 0097h. In reading through these addresses (0090h to 0097h) the bus
master will receive the individual bits of the registration number in exactly the same sequence as with a
ROM function command.
ADDRESS REGISTERS Figure 6
Bit # 7 6 5 4 3 2 1 0
T2 T1 T0
Target Address (TA1) T7 T6 T5 T4 T3 (0) (0) (0)
Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8
Ending Address with
Data Status (E/S) AA 1 PF 1
(Read Only)
E2 E1 E0
1 (1) (1) (1)
ADDRESS REGISTERS AND TRANSFER STATUS
The DS2432 employs three address registers: TA1, TA2 and E/S (Figure 6). These registers are common
to many other 1-Wire devices but operate slightly differently with the DS2432. Registers TA1 and TA2
must be loaded with the target address to which the data will be written or from which data will be read.
Register E/S is a read-only transfer-status register, used to verify data integrity with write commands.
Since the scratchpad of the DS2432 is designed to accept data in blocks of eight bytes only, the lower
three bits of TA1 will be forced to 0 and the lower three bits of the E/S register (Ending Offset) will
always read 1. This indicates that all the data in the scratchpad will be used for a subsequent copying into
main memory or secret. Bit 5 of the E/S register, called PF or “partial byte flag”, is a logic-1 if the
5 of 30
5 Page 
PRELIMINARY
Memory and SHA Functions Flow Chart (continued) Figure 7
DS2432
From Figure 7
3rd Part
33h
Compute Next
Secret ?
Y
Bus Master TX
TA1 (T7:T0),
TA2 (T15:T8)
N
N
Valid Data
Y
Address ?
Bus Master
RX “1”s
Master
TX Reset ?
Y
N
To Figure 7
5th Part
Note: The master must first
load the scratchpad with a
partial secret of 8 bytes
Y Write-
Protected ?
N
SHA Engine Computes Message
Authentication Code of Current
Secret, Page Data, and 8 Byte
Partial Secret in Scratchpad
*
DS2432 Copies a Partial MAC *
to the Secret Register
DS2432 fills Scratchpad with AAh
DS2432 TX “0”
Master
TX Reset ?
N
DS2432 TX “1”
Y
N Master
TX Reset ?
Y
To Figure 7
3rd Part
*
1-Wire idle high for power
From Figure 7
5th Part
11 of 30
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS2432.PDF ] | |
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