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PDF DS2423 Data sheet ( Hoja de datos )
| Número de pieza | DS2423 | |
| Descripción | 4kbit 1-Wire RAM with Counter | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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FEATURES
§ 4096 bits of SRAM
§ Four 32-bit, read-only counters
§ Active-low external trigger inputs for two of
the counters with on-chip debouncing
compatible with reed and Wiegand switches
§ Unique, factory-lasered and tested 64-bit
registration number (8-bit family code + 48-
bit serial number + 8-bit CRC tester) assures
absolute traceability because no two parts are
alike
§ Memory partitioned into 16 256-bit pages in
for packetizing data
§ 256-bit scratchpad with strict read/write
protocols ensures integrity of data transfer
§ On-chip 16-bit CRC generator for
safeguarding data transfers
§ Built-in multidrop controller ensures
compatibility with other MicroLAN products
§ Directly connects to a single port pin of a
microprocessor and communicates at up to
16.3kbits per second
§ Overdrive mode boosts communication speed
to 142kbits per second
§ 8-bit family code specifies device
communication requirements to reader
DS2423
4kbit 1-Wire
RAM with Counter
§ Presence detector acknowledges when reader
first applies voltage
§ Compact, low cost 6-pin TSOC surface mount
package
§ Reads, writes and counts over a wide voltage
range of 2.8V to 5.5V from -40°C to +85°C
PIN ASSIGNMENT
TSOC PACKAGE
16
25
34
TOP VIEW
3.7mm x 4.0mm x 1.5mm
SIDE VIEW
PIN DESCRIPTION
Pin 1
Ground
Pin 2
Data
Pin 3
Vbat
Pin 4
NC
Pin 5
Input channel B
Pin 6
Input channel A
ORDERING INFORMATION
DS2423P
6-pin TSOC package
DS2423P/T&R
Tape & Reel Version of
DS2423P
DS2423X
Chip Scale Pkg., Tape &
Reel
DESCRIPTION
The DS2423 1-Wire® RAM with Counters is a fully static, read/write memory for battery operation in a
low-cost, six-lead TSOC, surface-mount package. The memory is organized as 16 pages of 256 bits each.
In addition, the device has four counters, two of them with external trigger inputs called A and B. Each of
the counters is associated with a memory page. A counter without external trigger input increments each
time data is written to the page it is associated with (write cycle counter). The counters triggered by
inputs A and B, respectively, increment with every low-going pulse on their input. All counters are read-
only. They are automatically cleared to 0 when the battery is connected.
1-Wire is a registered trademark of Dallas Semiconductor.
1 of 25
060603
1 page  
DS2423
WRITING WITH VERIFICATION
To write data to the DS2423, the scratchpad has to be used as intermediate storage. First the master issues
the Write Scratchpad command to specify the desired target address, followed by the data to be written to
the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an
inverted CRC16 of the command, address and data at the end of the Write Scratchpad command
sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to
decide if the communication was successful and proceed to the Copy Scratchpad command. If the master
could not receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to
verify data integrity. As preamble to the scratchpad data, the DS2423 repeats the target address TA1 and
TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the
scratchpad. The master does not need to continue reading; it can start a new trial to write data to the
scratchpad. Similarly, a set AA flag indicates that the Write command was not recognized by the device.
If everything went correctly, both flags are cleared and the ending offset indicates the address of the last
byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After
the master has verified the data, it has to send the Copy Scratchpad command. This command must be
followed exactly by the data of the three address registers TA1, TA2 and E/S. The master may obtain the
contents of these registers by reading the scratchpad or derive it from the target address and the amount of
data to be written. As soon as the DS2423 has received these bytes correctly, it will copy the data to the
requested location beginning at the target address.
MEMORY FUNCTION COMMANDS
The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory.
An example follows the flowchart. The communication between master and DS2423 takes place either at
regular speed (default, OD = 0) or at Overdrive speed (OD = 1). If not explicitly set into the Overdrive
mode the DS2423 assumes regular speed.
Write Scratchpad Command [0FH]
After issuing the Write Scratchpad command, the master must first provide the 2-byte target address,
followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at
the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the master stops
writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be
ignored and the partial byte flag PF will be set.
When executing the Write Scratchpad command the CRC generator inside the DS2423 (see Figure 12)
calculates a CRC over the entire data stream, starting at the command code and ending at the last data
byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC
generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target
Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write
Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read
time slots and will receive the CRC generated by the DS2423.
The memory address range of the DS2423 is 0000H to 01FFH. If the bus master sends a target address
higher than this, the internal circuitry of the chip will set seven most significant address bits to 0 as they
are shifted into the internal address register. The Read Scratchpad command will reveal the target address
as it will be used by the DS2423. The master will identify such address modifications by comparing the
target address read back to the target address transmitted. If the master does not read the scratchpad, a
subsequent Copy Scratchpad command will not work since the most significant bits of the target address
the master sends will not match the value the DS2423 expects.
5 of 25
5 Page 
MEMORY FUNCTION FLOW CHART Figure 7 cont’d
DS2423
From Figure 7
2nd Part
A5H
Read Memory
+ Counter
Y
Master TX
TA1 (T7:T0)
N
1)
Master TX
TA2 (T15:T8)
1)
DS2423 Sets Memory
Address = (T15:T0)
Master RX Data
From Memory
1)
Y
Master
2)
TX Reset?
N
End of
Page?
N
Y
Master RX Counter 1)
Value of Memory Page
Master RX 32 Zero Bits 1)
DS2423 Increments
Address Counter
N
Master RX CRC 16 of Command, Address,
Data, Counter, Zero Bits (1st Pass)
CRC 16 of Data, Counter, Zero Bits
(Subsequent Passes)
1)
Master TX 2)
Reset
N
CRC
Correct?
Y
End of
Memory?
N
To Figure 7
2nd Part
Y
Master
TX Reset?
2)
Y
Master RX "1"s
N
1)
1) To be transmitted or received at Overdrive speed if OD = 1.
2) Reset Pulse to be transmitted at Overdrive speed if OD = 1.
Reset Pulse to be transmitted at normal speed if OD = 0 or if
the DS2423 is to be reset from Overdrive speed to regular
speed.
2)
Master
TX Reset?
Y
11 of 25
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet DS2423.PDF ] | |
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