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DS2411 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2411
Beschreibung Silicon Serial Number with VCC Input
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 11 Seiten
DS2411 Datasheet, Funktion
www.maxim-ic.com
FEATURES
§ Unique, Factory-Lasered and Tested 64-Bit
Registration Number (8-Bit Family Code
Plus 48-Bit Serial Number Plus 8-Bit CRC
Tester); Guaranteed No Two Parts Alike
§ Standby Current <1µA
§ Built-In Multidrop Controller Enables
Multiple DS2411s to Reside on a Common
1-Wireâ Network
§ Multidrop Compatible with Other 1-Wire
Products
§ 8-Bit Family Code Identifies Device as
DS2411 to the 1-Wire Master
§ Low-Cost TSOC, SOT23-3, and Flip-Chip
Surface-Mount Packages
§ Directly Connects to a Single-Port Pin of a
Microprocessor and Communicates at up to
15.4kbps
§ Overdrive Mode Boosts Communication
Speed to 125kbps
§ Operating Range: 1.5V to 5.25V, -40°C to
+85°C
DS2411
Silicon Serial Number with VCC Input
PIN CONFIGURATION
3
12
SOT23-3, Top View
16
25
34
TSOC, Top View
1
2
AB
Flip Chip, Top view, bumps
not visible
ORDERING INFORMATION
PART
DS2411R/
T&R
DS2411P
DS2411P/
T&R
DS2411X
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PACKAGE
SOT23-3,
Tape-and-Reel
TSOC
TSOC,
Tape-and-Reel
Flip Chip,
Tape-and-Reel
PIN DESCRIPTION
PIN
NAME SOT23 TSOC
I/O
VCC
GND
N.C.
N.C.
N.C.
1
2
3
2
6
1
3
4
5
FLIP
CHIP
A1
B2
B1
A2
DESCRIPTION
The DS2411 silicon serial number is a low-cost, electronic registration number with external power
supply. It provides an absolutely unique identity that can be determined with a minimal electronic
interface (typically, a single port pin of a microcontroller). The DS2411’s registration number is a
factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit
family code (01h). Data is transferred serially through the Dallas Semiconductor’s 1-Wire protocol. The
external power supply is required, extending the operating voltage range of the device below typical
1-Wire devices.
1-Wire is a registered trademark of Dallas Semiconductor.
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052003






DS2411 Datasheet, Funktion
TRANSACTION SEQUENCE
The communication sequence for accessing the DS2411 through the 1-Wire bus is as follows:
DS2411
§ Initialization
§ ROM Function Command
§ Read Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that the DS2411 is on the bus and is ready to
operate. For more details, see the 1-Wire Signaling section.
ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the three ROM function commands. All
ROM function command codes are 1 byte long. A list of these commands follows (see the flowchart in
Figure 5).
Read ROM [33h]
This command allows the bus master to read the DS2411’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command should only be used if there is a single slave device on the bus. If
more than one slave is present on the bus, a data collision results when all slaves try to transmit at the
same time (open drain produces a wired-AND result), and the resulting registration number read by the
master will be invalid.
Search ROM [F0h]
When a system is initially brought up, the bus master might not know the number of devices on the
1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the
master can use a process of elimination to identify the registration numbers of all slave devices. For each
bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time
slots. On the first slot, each slave device participating in the search outputs the true value of its
registration number bit. On the second slot, each slave device participating in the search outputs the
complemented value of its registration number bit. On the third slot, the master writes the true value of
the bit to be selected. All slave devices that do not match the bit written by the master stop participating
in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of
the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete
pass, the bus master knows the registration number of a single device. Additional passes identify the
registration numbers of the remaining devices. Refer to App Note 187: 1-Wire Search Algorithm for a
detailed discussion, including an example.
Overdrive Skip ROM [3Ch]
This command causes all overdrive-capable slave devices on the 1-Wire network to enter overdrive speed
(OD = 1). All communication following this command has to occur at overdrive speed until a reset pulse
of minimum 480ms duration resets all devices on the bus to regular speed (OD = 0).
To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed has to be
issued followed by a read ROM or search ROM command sequence. Overdrive speeds up the time for the
search process.
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