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PDF DS2229 Data sheet ( Hoja de datos )
| Número de pieza | DS2229 | |
| Descripción | Word-Wide 8 Meg SRAM Stik | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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DS2229
Word-Wide 8 Meg SRAM Stik
FEATURES
Organized as a high density 512k x 16 bit
StikTM
Fast access time of 85 ns
Unlimited write cycles
Employs popular JEDEC standard 80-position
SIMM connector
Full ±10% operating range
Read cycle time equals write cycle time
Ultra-low standby current < 10 µA
Suitable for battery-backed applications
PIN ASSIGNMENT
DESCRIPTION
80-PIN SIP STIK
The DS2229 is an 8,388,608-bit low-power fully static Random Access Memory organized as a 524,888
word by 16 bits using CMOS technology. The device employs the popular JEDEC standard 80-pin SIMM
connection scheme with no additional circuitry required. The device operates from a single power supply
with a voltage input of 4.5 to 5.5 volts. The Chip Enable inputs ( CE0 , CE1 , CE2 , CE3 ) are used for
device selection and can be used in order to achieve the minimum standby current mode which facilitates
battery backup. The device provides a fast access time of 85 ns. The DS2229 maintains TTL levels over
input voltage range 4.5V to 5.5V. The DS2229 is JEDEC pin compatible (see Figure 1) with flash
EEPROM memory SIMM boards of similar density.
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LOW VCC DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL MIN TYP MAX UNITS
VCC for Data Retention
VDR 2.0 - -
V
Data Retention Current
ICCDR
- 1 8 µA
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
0 - - ns
5 - - ms
DS2229
(tA= 0°C to 70°C)
TEST CONTIDION
CE0 - CE3 ≥ VCC -0.2V,
CS ≥ VCC -0.2V or 0V
≤ CS ≤ 0.2V VIN ≥ 0V
VCC = 3.0V, VIN ≥ 0V
CE0 - CE3 ≥ VCC -0.2V,
CS ≥ VCC -0.2V or 0V ≤
CS ≤ 0.2V tA =25°C
See Retention
Waveform
LOW VCC DATA RETENTION TIMING WAVEFORM (1) (CE0 - CE3 Controlled)
Figure 3
SEE NOTE 5
LOW VCC DATA RETENTION TIMING WAVEFORM (2) (CS Controlled) Figure 4
SEE NOTE 5
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet DS2229.PDF ] | |
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