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DS2224 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2224
Beschreibung EconoRAM
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 10 Seiten
DS2224 Datasheet, Funktion
DS2223/DS2224
DS2223/DS2224
EconoRAM
FEATURES
Low–cost, general–purpose, 256–bit memory
– DS2223 has 256–bit SRAM
– DS2224 has 32–bit ROM, 224–bit SRAM
Reduces control, address and data interface to a
single pin
Each DS2224 32–bit ROM is factory–lasered with a
unique serial number
DS2224 portion of ROM with custom code and unique
serial number available
Minimal operating power: 45 nanocoulombs per
transaction @1.5V typical
Less than 15 nA standby current at 25°C
Nonvolatile data retention easily achieved via low–
cost alkaline batteries or capacitors
Directly connects to a port pin of popular microcontrol-
lers
Operation from 1.2 to 5.5 volts
Popular TO–92 or SOT–223 surface mount package
Operates over industrial temperature range –40°C to
+85°C
PACKAGE OUTLINE
TO–92
12 3
SOT–223
1
123
BOTTOM VIEW
See Mech. Drawings
Section
24 3
TOP VIEW
See Mech. Drawings
Section
PIN CONNECTIONS
Pin 1 GND – Ground
Pin 2 DQ
– Data In/Out
Pin 3
Pin 4
VCC
GND
– Supply
– Ground
DESCRIPTION
The DS2223 and DS2224 EconoRAMs are fully static,
micro–powered, read/write memories in low–cost
TO–92 or SOT–223 packages. The DS2223 is orga-
nized as a serial 256 x 1 bit static read/write memory.
The DS2224’s first 32 bits are lasered with a unique ID
code at the time of manufacture; the remaining 224 bits
are static read/write memory. Signaling necessary for
reading or writing is reduced to just one interface lead.
Both the DS2223 and DS2224 are not recommended
for new designs. However, the parts will remain avail-
able until the year 2003, at least.
ORDERING INFORMATION
DS2223
DS2223Z
DS2223T
DS2223Y
DS2224
DS2224Z
DS2224T
DS2224Y
256–bit SRAM – TO–92 Package
256–bit SRAM – SOT–223 Package
1000 piece tape–and–reel of DS2223
2500 piece tape–and–reel of DS2223Z
32–bit serial number (ROM), 224–bit
SRAM – TO–92 Package
32–bit serial number (ROM), 224–bit
SRAM – SOT–223 Package
1000 piece tape–and–reel of DS2224
2500 piece tape–and–reel of DS2224Z
080598 1/10






DS2224 Datasheet, Funktion
DS2223/DS2224
1–WIRE INTERFACE
The 1–Wire interface has only a single line by definition;
it is important that host and EconoRAM be able to drive it
at the appropriate time. The EconoRAM is an open drain
part with an internal circuit equivalent to that shown in
Figure 8. The host can be the same equivalent circuit. If
a bidirectional pin is not available, separate output and
input pins can be tied together.
The 1–Wire interface requires a pull–up resistor with a
value of approximately 5 kto system VCC on the data
signal line. The EconoRAM has an internal open–drain
driver with a 500 kpull–down resistor to ground. The
open–drain driver allows the EconoRAM to be powered
by a small standby energy source, such as a single 1.5
volt alkaline battery, and still have the ability to produce
CMOS/TTL output levels. The pull–down resistor holds
the DQ pin at ground when the EconoRAM is not con-
nected to the host.
APPLICATION EXAMPLES
EconoRAMs are extremely conservative with power.
Data can be retained in these small memories for as
long as a month using the energy stored in a capacitor.
Data is retained as long as the voltage on the VCC pin of
the EconoRAM (VCAP) is at least 1.2 volts. A typical cir-
cuit is shown in Figure 9.
When VCC is applied, capacitor C1 is charged and the
EconoRAM receives power directly from VCC. After
power is removed, the diode CR1 prevents current from
leaking back into the system, keeping the capacitor
charged.
In the standby mode, the EconoRAM typically con-
sumes only 12 nA at 25°C. However, the power–down
process of the system can cause a slightly higher cur-
rent drain. This is due to the fact that as system power
ramps down, the signal attached to the DQ pin of the
EconoRAM transitions slowly through the linear region,
while the VCAP voltage remains at its initial value. While
in this region, the part draws more current as a function
of the DQ pin voltage (see Figure 10).
The data retention time can be estimated with the aid of
Figure 11. In this figure, the vertical axis represents the
value of the capacitor C1; the horizontal axis is the data
retention time in hours. The two curves represent initial
VCAP voltages of 3 and 5 volts. These curves are based
on the assumption that the time the DQ pin is in the lin-
ear region is less than 100 ms.
HOST TO ECONORAM INTERFACE Figure 8
VCC
5 k
VCC
TX
OPEN
DRAIN
RX
500 k
RX
100 OHM MOSFET
TX
HOST ECONORAM
080598 6/10

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