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DS21Q50LN Schematic ( PDF Datasheet ) - Maxim Integrated Products

Teilenummer DS21Q50LN
Beschreibung Quad E1 Transceiver
Hersteller Maxim Integrated Products
Logo Maxim Integrated Products Logo 




Gesamt 30 Seiten
DS21Q50LN Datasheet, Funktion
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21Q50 E1 quad transceiver contains all the
necessary functions for connecting to four E1 lines.
The on-board clock/data recovery circuitry coverts
the AMI/HDB3 E1 waveforms to an NRZ serial
stream. The DS21Q50 automatically adjusts to E1
22AWG (0.6mm) twisted-pair cables from 0km to
over 2km in length. The device can generate the
necessary G.703 waveshapes for both 75W coax and
120W twisted-pair cables. The on-board jitter
attenuators (selectable to either 32 bits or 128 bits)
can be placed in either the transmit or receive data
paths. The framers locate the frame and multiframe
boundaries and monitor the data streams for alarms.
The device contains a set of internal registers, from
which the user can access and control the operation
of the unit by the parallel control port or serial port.
The device fully meets all the latest E1 specifications
including ITU-T G.703, G.704, G.706, G.823, G.732,
and I.431 ETS 300 011, ETS 300 233, and ETS 300
166 as well as CTR12 and CTR4.
APPLICATIONS
DSLAMs
Routers
IMA and WAN Equipment
PIN CONFIGURATION
TOP VIEW
DS21Q50
100
1
LQFP
DS21Q50
Quad E1 Transceiver
FEATURES
§ Four Complete E1 (CEPT) PCM-30/ISDN-PRI
Transceivers
§ Long-Haul and Short-Haul Line Interfaces
§ 32-Bit or 128-Bit Crystal-Less Jitter Attenuator
§ Frames to FAS, CAS, CCS, and CRC4 Formats
§ 4MHz/8MHz/16MHz Clock Synthesizer
§ Flexible System Clock with Automatic Source
Switching on Loss-of-Clock Source
§ Two-Frame Elastic-Store Slip Buffer on the
Receive Side
§ Interleaving PCM Bus Operation Up to
16.384MHz
§ Configurable Parallel and Serial Port Operation
§ Detects and Generates Remote and AIS Alarms
§ Fully Independent Transmit and Receive
Functionality
§ Four Separate Loopback Functions
§ PRBS Generation/Detection/Error Counting
§ 3.3V Low-Power CMOS
§ Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and
E Bits
§ Eight Additional User-Configurable Output Pins
§ 100-Pin, 14mm x 14mmLQFP Package
ORDERING INFORMATION
PART
DS21Q50L
DS21Q50LN
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
100 LQFP (14mm)
100 LQFP (14mm)
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS21Q50LN Datasheet, Funktion
DS21Q50
1. INTRODUCTION
The DS21Q50 is optimized for high-density termination of E1 lines. Two significant features are included
for this type of application: the interleave bus option (IBO) and a system clock synthesizer feature. The
IBO allows up to eight E1 data streams to be multiplexed onto a single high-speed PCM bus without
additional external logic. The system clock synthesizer feature allows any of the E1 lines to be selected as
the master source of clock for the system and for all the transmitters. This is also accomplished without
the need of external logic. Each of the four transceivers has a clock and data jitter attenuator that can be
assigned to either the transmit or receive path. In addition there is a single, undedicated clock jitter
attenuator that can be hardware configured as the user needs. Each transceiver also contains a PRBS
pattern generator and detector. Figure 18-1 shows a simplified typical application that terminates eight E1
lines (transmit and receive pairs) and combines the data into a single 16.384MHz PCM bus. The
16.384MHz system clock is derived and phased-locked to one of the eight E1 lines. On the receive side of
each port, an elastic store provides logical management of any slip conditions because of the
asynchronous relationship of the eight E1 lines. In this application, all eight transmitters are timed to the
selected E1 line.
The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP
pins of the DS21Q50. The device recovers clock and data from the analog signal and passes it through the
jitter attenuation mux to the receive framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS21Q50 contains an active filter that reconstructs the analog received
signal for the nonlinear losses that occur in transmission. The device has a usable receive sensitivity of
0dB to -43dB, which allows the device to operate on cables over 2km in length. The receive framer
locates FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms
including, carrier loss, loss of synchronization, AIS, and remote alarm. If needed, the receive elastic store
can be enabled in order to absorb the phase and frequency differences between the recovered E1 data
stream and an asynchronous backplane clock which is provided at the SYSCLK input. The clock applied
at the SYSCLK input can be either a 2.048MHz/4.096MHz/8.192MHz or 16.384MHz clock. The
transmit framer is independent from the receive in both the clock requirements and characteristics. The
transmit formatter provides the necessary frame/multiframe data overhead for E1 transmission.
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DS21Q50LN pdf, datenblatt
DS21Q50
Table 2-2. Pin Assignment (by LQFP Pin Number)
NAME
PIN
PARALLEL PORT
ENABLED
SERIAL
PORT
ENABLED
TYPE
FUNCTION
[Serial Port Mode in Brackets]
1 TTIP4
O Transmit Analog Tip Output
2 TVSS4
— Transmit Analog Signal Ground
3 TVDD4
— Transmit Analog Positive Supply
4 TRING4
O Transmit Analog Ring Output
5 TCLK4
I Transmit Clock
6 TSER4
I Transmit Serial Data
7 TSYNC4
I/O Transmit Sync
8 DVSS4
— Digital Signal Ground
9 DVDD4
— Digital Positive Supply
10 OUTB3
O User Selectable Output B
11 OUTA3
O User Selectable Output A
12 SYSCLK3
I Transmit/Receive System Clock
13 RSER3
O Receive Serial Data
14 RSYNC3
I/O Receive Sync
15 RVSS4
— Receive Analog Signal Ground
16 RTIP3
I Receive Analog Tip Input
17 RRING3
I Receive Analog Ring Input
18 RVDD4
— Receive Analog Positive Supply
19 D0/AD0
I/O Data Bus Bit0/Address/Data Bus Bit 0
20 D1/AD1
I/O Data Bus Bit1/ Address/Data Bus Bit 1
21 D2/AD2
I/O Data Bus Bit 2/Address/Data Bus Bit2
22 D3/AD3
I/O Data Bus Bit 3/Address/Data Bus Bit 3
23 D4/AD4
I/O Data Bus Bit4/Address/Data Bus Bit 4
24 D5/AD5
I/O Data Bus Bit 5/Address/Data Bus Bit 5
25 D6/AD6
I/O Data Bus Bit 6/Address/Data Bus Bit 6
26 TTIP3
O Transmit Analog Tip Output
27 TVSS3
— Transmit Analog Signal Ground
28 TVDD3
— Transmit Analog Positive Supply
29 TRING3
O Transmit Analog Ring Output
30 TCLK3
I Transmit Clock
31 TSER3
I Transmit Serial Data
32 TSYNC3
I/O Transmit Sync
33 DVSS3
— Digital Signal Ground
34 DVDD3
— Digital Positive Supply
35 OUTB2
O User Selectable Output B
36 OUTA2
O User Selectable Output A
37 SYSCLK2
I Transmit/Receive System Clock
38 RSER2
O Receive Serial Data
39 RSYNC2
I/O Receive Sync
40 RVSS3
— Receive Analog Signal Ground
41 RTIP2
I Receive Analog Tip Input
42 RRING2
I Receive Analog Ring Input
43 RVDD3
— Receive Analog Positive Supply
44 D7/AD7
SDO
I/O Data Bus Bit 7/Address/Data Bus Bit 7
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