Datenblatt-pdf.com


DS21Q42TN Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS21Q42TN
Beschreibung Enhanced QUAD T1 FRAMER
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 30 Seiten
DS21Q42TN Datasheet, Funktion
DS21Q42
Enhanced QUAD T1 FRAMER
www.dalsemi.com
FEATURES
Four T1 DS1/ISDN–PRI/J1 framing
transceivers
All four framers are fully independent
Each of the four framers contain dual two–
frame elastic store slip buffers that can connect
to asynchronous backplanes up to 8.192 MHz
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Programmable output clocks for Fractional T1
Fully independent transmit and receive
functionality
Integral HDLC controller with 64-byte buffers
configurable for FDL or DS0 operation
Generates and detects in–band loop codes from
1 to 8 bits in length including CSU loop codes
Pin compatible with DS21Q44 E1 Enhanced
Quad E1 Framer
3.3V supply with 5V tolerant I/O; low power
CMOS
Available in 128–pin TQFP package
IEEE 1149.1 support
FUNCTIONAL DIAGRAM
Receive
Framer
Elastic
Store
Transmit
Formatter
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
Elastic
Store
Control Port
ACTUAL SIZE
QUAD
T1
FRAMER
ORDERING INFORMATION
DS21Q42T (00 C to 700 C)
DS21Q42TN (-400 C to +850 C)
DESCRIPTION
The DS21Q42 is an enhanced version of the DS21Q41B Quad T1 Framer. The DS21Q42 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q42 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest T1 specifications including ANSI T1.403–1995, ANSI T1.231–1993,
AT&T TR 62411 (12–90), AT&T TR54016, and ITU G.704 and G.706.
1 of 119
031500






DS21Q42TN Datasheet, Funktion
DS21Q42
14. HDLC CONTROLLER................................................................................................................... 59
14.1. HDLC FOR DS0S ................................................................................................................... 59
15. FDL/FS EXTRACTION AND INSERTION.................................................................................. 60
15.1. HDLC AND BOC CONTROLLER FOR THE FDL .............................................................. 60
15.1.1. General Overvie ............................................................................................................ .60
15.1.2. Status Register for the HDLC ........................................................................................ 61
15.1.3. HDLC/BOC Register Description ................................................................................. 63
15.2. LEGACY FDL SUPPORT ...................................................................................................... 71
15.2.1. Ov_2.1.71...................................................................................................................... 71
15.2.2. Receive Section............................................................................................................. 71
15.2.3. Transmit Section ........................................................................................................... 72
15.2.4. D4/SLC–96 OPERATION ............................................................................................ 73
16. PROGRAMMABLE IN–BAND CODE GENERATION AND DETECTION.......................... 73
17. TRANSMIT TRANSPARENCY .................................................................................................... 76
18. INTERLEAVED PCM BUS OPERATION ................................................................................... 76
19. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................... 79
19.1. DESCRIPTION ....................................................................................................................... 79
19.2. TAP CONTROLLER STATE MACHINE.............................................................................. 80
19.3. INSTRUCTION REGISTER AND INSTRUCTIONS ........................................................... 82
19.4. TEST REGISTERS ................................................................................................................. 84
20. TIMING DIAGRAMS ...................................................................................................................... 89
21. OPERATING PARAMETERS .................................................................................................... 104
22. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................ 119
6 of 119

6 Page









DS21Q42TN pdf, datenblatt
Pin Description Sorted by Pin Function, FMS = 0 Table 2-2
PIN SYMBOL TYPE DESCRIPTION
108
8MCLK
O 8 MHz Clock
23 A0 I Address Bus Bit 0; LSB
24 A1 I Address Bus Bit 1
25 A2 I Address Bus Bit 2
26 A3 I Address Bus Bit 3
27 A4 I Address Bus Bit 4
28 A5 I Address Bus Bit 5
29
A6/ALE (AS)
I Address Bus Bit 6; MSB or Address Latch Enable
(Address Strobe)
46 A7 I Address Bus Bit 7
61 BTS I Bus Type Select for Parallel Control Port
112
CLKSI
I 8MCLK Clock Reference Input
60 CS* I Chip Select
117
D0 or AD0
I/O Data Bus Bit or Address/Data Bit 0; LSB
118
D1 or AD1
I/O Data Bus Bit or Address/Data Bit 1
119
D2 or AD2
I/O Data Bus Bit or Address/Data Bit 2
120
D3 or AD3
I/O Data Bus Bit or Address/Data Bit 3
121
D4 or AD4
I/O Data Bus Bit or Address/Data Bit 4
122
D5 or AD5
I/O Data Bus Bit or Address/Data Bit 5
123
D6 or AD6
I/O Data Bus Bit or Address/Data Bit 6
124
D7 or AD7
I/O Data Bus Bit or Address/Data Bit 7; MSB
47
FMS
I Framer Mode Select
58 FS0 I Framer Select 0 for Parallel Control Port
59 FS1 I Framer Select 1 for Parallel Control Port
30
INT*
O Receive Alarm Interrupt for all Four Framers
52
JTCLK
I JTAG Test Clock
84
JTDI
I JTAG Test Data Input
86
JTDO
O JTAG Test Data Output
50
JTMS
I JTAG Test Mode Select
18
JTRST*
I JTAG Reset
64
MUX
I Non-Multiplexed or Multiplexed Bus Select
10
RCHBLK0
O Receive Channel Block from Framer 0
44
RCHBLK1
O Receive Channel Block from Framer 1
80
RCHBLK2
O Receive Channel Block from Framer 2
104
RCHBLK3
O Receive Channel Block from Framer 3
6
RCLK0
I Receive Clock for Framer 0
40
RCLK1
I Receive Clock for Framer 1
74
RCLK2
I Receive Clock for Framer 2
100
RCLK3
I Receive Clock for Framer 3
62
RD*/(DS*)
I Read Input (Data Strobe)
17
RFSYNC0
O Receive Frame Sync from Framer 0
51
RFSYNC1
O Receive Frame Sync from Framer 1
85
RFSYNC2
O Receive Frame Sync from Framer 2
109
RFSYNC3
O Receive Frame Sync from Framer 3
5
RLCLK0
O Receive Link Clock from Framer 0
12 of 119
DS21Q42

12 Page





SeitenGesamt 30 Seiten
PDF Download[ DS21Q42TN Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
DS21Q42TEnhanced QUAD T1 FRAMERDallas Semiconducotr
Dallas Semiconducotr
DS21Q42TNEnhanced QUAD T1 FRAMERDallas Semiconducotr
Dallas Semiconducotr

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche