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DS21Q41B Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS21Q41B
Beschreibung Quad T1 Framer
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 30 Seiten
DS21Q41B Datasheet, Funktion
www.dalsemi.com
DS21Q41B
Quad T1 Framer
FEATURES
§ Four T1 DS1/ISDN-PRI framing transceivers
§ All four framers are fully independent
§ Frames to D4, ESF, and SLC-96 formats
§ 8-bit parallel control port that can be
connected to either multiplexed or non-
multiplexed buses
§ Each of the four framers contains dual two-
frame elastic stores that can connect to
asynchronous or synchronous backplanes up
to 8.192 MHz
§ Extracts and inserts robbed bit signaling
§ Framer and payload loopbacks
§ Large counters for BPVs, LCVs, EXZs,
CRC6, PCVs, F-bit errors and the number of
multiframes out of sync
§ Contains ANSI 1s density monitor and
enforcer
§ CSU loop code generator and detector
§ Programmable output clocks for Fractional
T1, ISDN-PRI, Actual Size and per channel
loopback applications
§ Onboard FDL support circuitry
§ Pin-compatible with DS21Q43 Quad E1
Framer
§ 5V supply; low power CMOS
§ Available in 128-pin TQFP
§ Industrial (-40°C to +85°C) grade version
available (DS21Q41BTN)
FUNCTIONAL DIAGRAM
RECEIVE
FRAMER
ELASTIC
STORE
TRANSMIT
FORMATTER
ELASTIC
STORE
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
CONTROL PORT
ACTUAL SIZE
QUAD
T1
FRAMER
DESCRIPTION
The DS21Q41B combines four of the popular DS2141A T1 Controllers onto a single monolithic die. The
“B” designation denotes that some new features are available in the Quad version that were not available
in the single T1 device. The added features in the DS21Q41B are listed in Section 1. The DS21Q41B
offers a substantial space savings to applications that require more than one T1 framer on a card. The
Quad version is only slightly bigger than the single T1 device. All four framers in the DS21Q41B are
totally independent; they do not share a common framing synchronizer. Also, the transmit and receive
sides of each framer are totally independent. The dual two-frame elastic stores contained in each of the
four framers can be independently enabled and disabled as required. The DS21Q41B meets all of the
latest specifications including ANSI T1.403 (and the emerging T1.403-199X), ANSI T1.231-1993,
AT&T TR62411, AT&T TR54016, ITU G.704 and G.706.
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DS21Q41B Datasheet, Funktion
102 RPOS3
7 RNEG0
41 RNEG1
75 RNEG2
101 RNEG3
12 RSYNC0
48 RSYNC1
82 RSYNC2
106 RSYNC3
17 RFSYNC0
51 RFSYNC1
85 RFSYNC2
109 RFSYNC3
16 RMSYNC0
50 RMSYNC1
84 RMSYNC2
108 RMSYNC3
11 RSYSCLK0
45 RSYSCLK1
81 RSYSCLK2
105 RSYSCLK3
18 RLOS/LOTC0
52 RLOS/LOTC1
86 RLOS/LOTC2
112 RLOS/LOTC3
DS21Q41B
I Receive Bipolar Data for Framer 3
I Receive Bipolar Data for Framer 0
I Receive Bipolar Data for Framer 1
I Receive Bipolar Data for Framer 2
I Receive Bipolar Data for Framer 3
I/O Receive Sync for Framer 0
I/O Receive Sync for Framer 1
I/O Receive Sync for Framer 2
I/O Receive Sync for Framer 3
O Receive Frame Sync from Framer 0
O Receive Frame Sync from Framer 1
O Receive Frame Sync from Framer 2
O Receive Frame Sync from Framer 3
O Receive Multiframe Sync from Framer 0
O Receive Multiframe Sync from Framer 1
O Receive Multiframe Sync from Framer 2
O Receive Multiframe Sync from Framer 3
I Receive System Clock for Elastic Store in Framer 0
I Receive System Clock for Elastic Store in Framer 1
I Receive System Clock for Elastic Store in Framer 2
I Receive System Clock for Elastic Store in Framer 3
O Receive Loss of Sync/Loss of Transmit Clock from Framer 0
O Receive Loss of Sync/Loss of Transmit Clock from Framer 1
O Receive Loss of Sync/Loss of Transmit Clock from Framer 2
O Receive Loss of Sync/Loss of Transmit Clock from Framer 3
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DS21Q41B pdf, datenblatt
ADDRESS
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
R/W
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REGISTER NAME
Receive Signaling Register 5
Receive Signaling Register 6
Receive Signaling Register 7
Receive Signaling Register 8
Receive Signaling Register 9
Receive Signaling Register 10
Receive Signaling Register 11
Receive Signaling Register 12
Receive Channel Blocking Register 1
Receive Channel Blocking Register 2
Receive Channel Blocking Register 3
Interrupt Mast Register 2
Transmit Signaling Register 1
Transmit Signaling Register 2
Transmit Signaling Register 3
Transmit Signaling Register 4
Transmit Signaling Register 5
Transmit Signaling Register 6
Transmit Signaling Register 7
Transmit Signaling Register 8
Transmit Signaling Register 9
Transmit Signaling Register 10
Transmit Signaling Register 11
Transmit Signaling Register 12
Test Register(2)
Test Register(2)
Transmit FDL Register
Interrupt Mask Register 1
DS21Q41B
NOTES:
1. Address 25 also contains Multiframe Out of Sync Count Register 1.
2. The Test Registers are used only by the factory; these registers must be cleared (set to all 0s) on
power-up initialization to insure proper operation.
3. Any unused register address will allow the status of the interrupts to appear on the bus.
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