PDF DS2186 Data sheet ( Hoja de datos )

Número de pieza	DS2186
Descripción	Transmit Line Interface
Fabricantes	Dallas Semiconducotr
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No Preview Available ! DS2186 DS2186 Transmit Line Interface FEATURES • Line interface for T1 (1.544 MHz) and CEPT (2.048 MHz) primary rate networks • On–chip transmit LBO (line build out) and line drivers eliminate external components • Programmable output pulse shape supports short– and long–loop applications • Supports bipolar and unipolar input data formats • Transparent B8ZS and HDB3 zero code suppression modes • Compatible with DS2180A T1 and DS2181A CEPT Transceivers DS2141A T1 and DS2143 E1 Control- lers • Companion to the DS2187 Receive Line Interface and DS2188 T1/CEPT Jitter Attenuator • Single 5V supply; low–power CMOS technology PIN ASSIGNMENT TAIS 1 20 LCLK ZCSEN 2 19 LPOS TCLKSEL 3 18 LNEG LEN0 4 17 TCLK LEN1 5 16 TPOS LEN2 6 15 TNEG VDD TTIP 7 8 14 LB 13 MTIP TRING 9 12 MRING VSS 10 11 LF 20–PIN DIP (300 MIL) TAIS ZCSEN TCLKSEL LEN0 LEN1 LEN2 VDD TTIP TRING VSS 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 LCLK LPOS LNEG TCLK TPOS TNEG LB MTIP MRING LF 20–PIN SOIC (300 Mil) DESCRIPTION The DS2186 T1/CEPT Transmit Line Interface Chip in- terfaces user equipment to North American (T1–1.544 MHz) and European (CEPT–2.048 MHz) primary rate communications networks. The device is compatible with all types of twisted pair and coax cable found in such networks. Key on–chip components include: programmable wave shaping circuitry, line drivers, remote loopback, and zero suppression logic. A line–coupling transformer is the only external component required. Short loop (DSX–1, 0 to 655 feet) and long loop (CSU; 0 dB, –7.5 dB and –15 dB) pulse templates found in T1 applications are supported. Appropriate CCITT recom- mendations are met in the CEPT mode. Application areas include DACS, CSU, CPE, channel banks, and PABX–to–computer interfaces such as DMI and CPI. The DS2186 supports ISDN–PRI (Primary Rate Interface) specifications. 022798 1/11 1 page DSX–1 ISOLATED PULSE TEMPLATE Figure 3 1.0 0.5 NORMALIZED ALITITUDE 0.0 DS2186 –0.5 0 250 500 750 1000 1250 NANOSECONDS NOTES: 1. Template shown is measured at the cross–connect point. 2. Amplitude shown is normalized; the actual midpoint voltage measured may be between 2.4 and 3.6 volts. 3. The corner points shown below are joined by straight lines to form the template. MAXIMUM CURVE (0, 0.05) (250, 0.05) (325, 0.80) (325, 1.15) (425, 1.15) (500, 1.05) (675, 1.05) (725, –0.07) (875, 0.05) (1250, 0.05) MINIMUM CURVE (0, –0.05) (350, –0.05) (350, 0.5) (400, 0.95) (500, 0.95) (600, 0.9) (650, 0.5) (650, –0.45) (800, –0.45) (925, –0.2) (1100, –0.05) (1250, –0.05) 022798 5/11 5 Page DS2186S TRANSMIT LINE INTERFACE 20–PIN SOIC KG 1 E A BH C phi J F L DS2186 PKG DIM A IN. MM B IN. MM C IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM L IN. MM phi 20–PIN MIN MAX 0.500 12.70 0.511 12.99 0.290 7.37 0.300 7.65 0.089 2.26 0.095 2.41 0.004 0.102 0.012 0.30 0.094 2.38 0.105 2.68 0.050 BSC 1.27 BSC 0.398 10.11 0.416 10.57 0.009 0.229 0.013 0.33 0.013 0.33 0.019 0.48 0.016 0.406 0° 0.040 1.20 8° 022798 11/11 11 Page

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