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DS2172 Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2172
Beschreibung Bit Error Rate Tester BERT
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 21 Seiten
DS2172 Datasheet, Funktion
www.dalsemi.com
FEATURES
Generates/Detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systems
Operates at speeds from DC to 52 MHz
Programmable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 26-1, 29-1, 211-1, 215-1, 220-1, 223-1,
and 232-1
Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in length
Large 32-bit error count and bit count
registers
Software programmable bit error insertion
Fully independent transmit and receive
sections
8-bit parallel control port
Detects test patterns with bit error rates up to
10-2
DS2172
Bit Error Rate Tester (BERT)
PIN ASSIGNMENT
TL
AD0
AD1
TEST
VSS
AD2
AD3
AD4
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 DS2172 21
5 32-Pin TQFP 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
RL
RLOS
LC
VSS
VDD
INT
WR(R/W)
ALE(AS)
ORDERING INFORMATION
DS2172T
(00 C to 700 C)
DS2172TN
(-400 C to + 850 C)
DESCRIPTION
The DS2172 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)
conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS2172 operates at clock rates
ranging from DC to 52 MHz. This wide range of operating frequency allows the DS2172 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.
The DS2172 user-programmable pattern registers provide the unique ability to generate loopback patterns
required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS2172 can initiate the
loopback, run the test, check for errors, and finally deactivate the loopback.
The DS2172 consists of four functional blocks: the pattern generator, pattern detector, error counter, and
control interface. The DS2172 can be programmed to generate any pseudorandom pattern with length up
to 232-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic
inputs can be used to configure the DS2172 for applications requiring gap clocking such as Fractional-T1,
Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the
DS2172 can insert single or 10-1 to 10-7 bit errors to verify equipment operation and connectivity.
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DS2172 Datasheet, Funktion
DS2172
2.0 PARALLEL CONTROL INTERFACE
The DS2172 is controlled via a multiplexed bi-directional address/data bus by an external microcontroller
or microprocessor. The DS2172 can operate with either Intel or Motorola bus timing configurations. If
the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All
Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical
Characteristics for more details. The multiplexed bus on the DS2172 saves pins because the address
information and data information share the same signal paths. The addresses are presented to the pins in
the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus
cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2172 latches
the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later
portion of the DS or WR pulses. In a read cycle, the DS2172 outputs a byte of data during the latter
portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance
state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The DS2172 can
also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update counters and
load transmit and receive pattern registers. At slow clock rates, sufficient time must be allowed for these
port operations.
3.0 PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
(MSB)
PS31 PS30 PS29 PS28
PS23 PS22 PS21 PS20
PS15 PS14 PS13 PS12
PS7 PS6 PS5 PS4
PS27
PS19
PS11
PS3
PS26
PS18
PS10
PS2
(LSB)
PS25 PS24
PS17 PS16
PS9 PS8
PS1 PS0
PSR3 (addr.=00 Hex)
PSR2 (addr.=01 Hex)
PSR1 (addr.=02 Hex)
PSR0 (addr.=03 Hex)
4.0 PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
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DS2172 pdf, datenblatt
BIT ERROR COUNT REGISTERS
(MSB)
(LSB)
BEC31 BEC30 BEC29 BEC28 BEC27 BEC26 BEC25 BEC24
BEC23 BEC22 BEC21 BEC20 BEC19 BEC18 BEC17 BEC16
BEC15 BEC14 BEC13 BEC12 BEC11 BEC10 BEC9 BEC8
BEC7 BEC6 BEC5 BEC4 BEC3 BEC2 BEC1 BEC0
DS2172
BECR3
(addr.=0C Hex)
BECR2
(addr.=0D Hex)
BECR1
(addr.=0E Hex)
BECR0
(addr.=0F Hex)
10.0 PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS2172. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS2172 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
PATTERN RECEIVE REGISTERS
(MSB)
PR31 PR30 PR29 PR28 PR27
PR23 PR22 PR21 PR20 PR19
PR15 PR14 PR13 PR12 PR11
PR7 PR6 PR5 PR4 PR3
PR26
PR18
PR10
PR2
PR25
PR17
PR9
PR1
(LSB)
PR24
PR16
PR8
PR0
PRR3 (addr.=10 Hex)
PRR2 (addr.=11 Hex)
PRR1 (addr.=12 Hex)
PRR0 (addr.=13 Hex)
11.0 STATUS REGISTER AND INTERRUPT MASK REGISTER
The Status Register (SR) contains information on the current real time status of the DS2172. When a
particular event has occurred, the appropriate bit in the register will be set to a 1. All of the bits in these
registers (except for the SYNC bit) operate in a latched fashion. This means that if an event occurs and a
bit is set to a 1 in any of the registers, it will remain set until the user reads that bit. For the BED, BCOF,
and BECOF status bits, they will be cleared when read and will not be set again until the event has
occurred again. For RLOS, RA0, and RA1 status bits, they will be cleared when read if the condition no
longer persists.
The SR register has the unique ability to initiate a hardware interrupt via the INT pin. Each of the alarms
and events in the SR can be either masked or unmasked from the interrupt pins via the Interrupt Mask
Register (IMR).
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