Datenblatt-pdf.com


DS2165-DS2165Q Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2165-DS2165Q
Beschreibung 16/24/32kbps ADPCM Processor
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 17 Seiten
DS2165-DS2165Q Datasheet, Funktion
www.maxim-ic.com
FEATURES
§ Compresses/expands 64kbps PCM voice
to/from either 32kbps, 24kbps, or 16kbps
§ Dual fully independent channel architecture;
device can be programmed to perform either:
- two expansions
- two compressions
- one expansion and one compression
§ Interconnects directly to combo-codec
devices
§ Input to output delay is less than 375ms
§ Simple serial port used to configure the
device
§ On-board time-slot assigner-circuit (TSAC)
function allows data to be input/output at
various time slots
§ Supports Channel Associated Signaling
§ Each channel can be independently idled or
placed into bypass
§ Available hardware mode requires no host
processor; ideal for voice storage
applications
§ Single +5V supply; low-power CMOS
technology
§ Available in 28-pin PLCC
§ 3V operation version is available
(DS2165QL)
DS2165Q
16/24/32kbps ADPCM Processor
PIN ASSIGNMENT (Top View)
NC
A0
A1
A2
A3
A4
A5
4 3 2 1 28 27 26
5 25
6 24
7 23
8 DS2165Q 22
9 21
10 20
11 19
12 13 14 15 16 17 18
FSY
YOUT
CS
SDI
SCLK
XOUT
NC
28-Pin PLCC
DESCRIPTION
The DS2165Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been
optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three
different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from)
either 32kbps, 24kbps, or 16kbps. The compression to 32kbps follows the algorithm specified by CCITT
Recommendation G.721 (July 1986) and ANSI document T1.301 (April 1987). The compression to
24kbps follows ANSI document T1.303. The compression to 16kbps follows a proprietary algorithm
developed by Dallas Semiconductor. The DS2165Q can switch compression algorithms on-the-fly. This
allows the user to make maximum use of the available bandwidth on a dynamic basis.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device errata,
click here: http://www.maxim-ic.com/errata.
1 of 17
070802






DS2165-DS2165Q Datasheet, Funktion
Table 2. ALGORITHM SELECT BITS
ALGORITHM SELECTED
AS2
64kbps to/from 32kbps
0
64kbps to/from 24kbps
1
64kbps to/from 16kbps
1
AS1
0
1
0
AS0
0
1
1
Figure 5. INPUT TIME SLOT REGISTER
(MSB)
— —- D5 D4 D3
D2
SYMBOL
D5
D4
D3
D2
D1
D0
POSITION
ITR.7
ITR.6
ITR.5
ITR.4
ITR.3
ITR.2
FUNCTION
Reserved. Must be 0 for proper operation
Reserved. Must be 0 for proper operation
MSB of input time slot register
ITR.1
ITR.0
LSB of input time slot register
Figure 6. OUTPUT TIME SLOT REGISTER
(MSB)
— — D5 D4 D3
D2
SYMBOL
D5
D4
D3
D2
D1
D0
POSITION
FUNCTION
OTR.7 Reserved. Must be 0 for proper operation
OTR.6 Reserved. Must be 0 for proper operation
OTR.5
OTR.4
OTR.3
OTR.2
OTR.1
OTR.0
MSB of output time slot register
LSB of output time slot register
6 of 17
DS2165Q
(LSB)
D1 D0
(LSB)
D1 D0

6 Page









DS2165-DS2165Q pdf, datenblatt
DS2165Q
TIME SLOT RESTRICTIONS
Under certain conditions, the DS2165Q does contain some restrictions on the output time slots that are
available. These restrictions are covered in detail in a separate application note. No restrictions occur if
the DS2165Q is operated in the hardware mode.
INPUT TO OUTPUT DELAY
With all three compressions algorithms, the total delay, from the time the PCM data sample is captured
by the DS2165Q to the time it is output, is always less than 375ms. The exact delay is determined by the
input and output time slots selected for each channel.
CHANNEL ASSOCIATED SIGNALING
The DS2165Q supports Channel Associated Signaling (CAS) through its ability to automatically change
from the 32kbps compression algorithm to the 24kbps algorithm. If the DS2165Q is configured to
perform the 32kbps algorithm, then in both the hardware and software mode it senses the frame sync
inputs (FSX and FSY) for a double-wide frame-sync pulse. Whenever the DS2165Q receives a double-
wide pulse, it automatically switches from the 32kbps algorithm to the 24kbps algorithm. Switching to
the 24kbps algorithm allows the user to insert signaling data into the LSB bit position of the ADPCM
output because this bit does not contain any useful speech information.
ON-THE-FLY ALGORITHM SELECTION
In the software mode, the user can switch between the three available algorithms on-the-fly. That is, the
DS2165Q does not need to be reset or stopped to make the change from one algorithm to another. The
DS2165Q reads the control register before it starts to process each PCM or ADPCM sample. If the user
wishes to switch algorithms, then the control register must be updated by the serial port before the first
input sample to be processed with the new algorithm arrives at either XIN or YIN. The PCM and
ACPCM outputs tri-state during register updates.
12 of 17

12 Page





SeitenGesamt 17 Seiten
PDF Download[ DS2165-DS2165Q Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
DS2165-DS2165Q16/24/32kbps ADPCM ProcessorDallas Semiconducotr
Dallas Semiconducotr

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche