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PDF DS21552LN Data sheet ( Hoja de datos )
| Número de pieza | DS21552LN | |
| Descripción | 3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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3.3V DS21352 and 5V DS21552
T1 Single-Chip Transceivers
FEATURES
§ Complete DS1/ISDN–PRI/J1 transceiver functionality
§ Long and Short haul LIU
§ Crystal–less jitter attenuator
§ Generates DSX–1 and CSU line build-outs
§ HDLC controller with 64-byte buffers Configurable for
FDL or DS0 operation
§ Dual two–frame elastic store slip buffers that can
connect to asynchronous backplanes up to 8.192MHz
§ 8.192MHz clock output locked to RCLK
§ Interleaving PCM Bus Operation
§ Per-channel loopback and idle code insertion
§ 8-bit parallel control port muxed or nonmuxed buses
(Intel or Motorola)
§ Programmable output clocks for Fractional T1
§ Fully independent transmit and receive functionality
§ Generates/detects in-band loop codes from 1 to 8 bits
in length including CSU loop codes
§ IEEE 1149.1 JTAG-Boundary Scan
§ Pin compatible with DS2152/54/354/554 SCTs
§ 100-pin LQFP package (14 mm x 14 mm) 3.3V
(DS21352) or 5V (DS21552) supply; low power
CMOS
PIN ASSIGNMENT
DS21352
DS21552
100
1
ORDERING INFORMATION
DS21352L
DS21352LN
DS21552L
DS21552LN
(0°C to +70°C)
(-40°C to +85°C)
(0°C to +70°C)
(-40°C to +85°C)
DESCRIPTION
The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1
lines whether they are DS1 long haul or DSX–1 short haul. The clock recovery circuitry automatically
adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX–1 line build
outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator
(selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The
framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also
used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of
internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12–90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
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1 page  
1. LIST OF FIGURES
DS21352/DS21552
Figure 3-1 SCT BLOCK DIAGRAM.........................................................................................................9
Figure 16-1 EXTERNAL ANALOG CONNECTIONS ..........................................................................87
Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS ..........................................................................88
Figure 16-3 TRANSMIT WAVEFORM TEMPLANE............................................................................89
Figure 16-4 JITTER TOLERANCE .........................................................................................................91
Figure 16-5 JITTER ATTENUATION ....................................................................................................91
Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552...........................................93
Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR TE DS21352..............................................94
Figure 16-8 TYPICAL MONITOR PORT APPLICATION....................................................................95
Figure 19-1 JTAG FUNCTIONAL BLOCK DIAGRAM......................................................................100
Figure 19-2 TAP CONTROLLER STATE DIAGRAM ........................................................................103
Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS ............................................................110
Figure 21-1 RECEIVE SIDE D4 TIMING.............................................................................................111
Figure 21-2 RECEIVE SIDE ESF TIMING...........................................................................................112
Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled)..............................113
Figure 21-4 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled) ...........113
Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) ...........114
Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE ..............................115
Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE ...........................116
Figure 21-8 TRANSMIT SIDE D4 TIMING .........................................................................................117
Figure 21-9 TRANSMIT SIDE ESF TIMING .......................................................................................118
Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) ........................119
Figure 21-11 TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)......119
Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)......120
Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE.........................121
Figure 21-14 TRANSMIT SIDE INTERLEAVE BUS OPERATION, FRAME MODE .....................122
Figure 22-1 RECEIVE DATA FLOW ...................................................................................................123
Figure 22-2 TRANSMIT DATA FLOW................................................................................................124
Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX=1) .............................................................127
Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) ...........................................................127
Figure 24-3 MOTOROLA BUS TIMING (BTS=1 / MUX=1)..............................................................128
Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX=0) ..............................................................130
Figure 24-5 INTEL BUS READ TIMING (BTS=0 / MUX=0) .............................................................130
Figure 24-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-7 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0)..................................................131
Figure 24-8 RECEIVE SIDE TIMING ..................................................................................................133
Figure 24-9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED...............................................134
Figure 24-10 RECEIVE LINE INTERFACE TIMING .........................................................................135
Figure 24-11 TRANSMIT SIDE TIMING.............................................................................................137
Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED .........................................138
Figure 24-13 TRANSMIT LINE INTERFACE TIMING......................................................................138
5 of 137
5 Page 
4. PIN DESCRIPTION
DS21352/DS21552
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER
PIN
SYMBOL
TYPE DESCRIPTION
1
RCHBLK
O Receive Channel Block
2
JTMS
I IEEE 1149.1 Test Mode Select
3
8MCLK
O 8.192 MHz Clock
4
JTCLK
I IEEE 1149.1 Test Clock Signal
5
JTRST
I IEEE 1149.1 Test Reset
6 RCL O Receive Carrier Loss
7
JTDI
I IEEE 1149.1 Test Data Input
8 NC – No Connect
9 NC – No Connect
10
JTDO
O IEEE 1149.1 Test Data Output
11 BTS I Bus Type Select
12
LIUC
I Line Interface Connect
13
8XCLK
O Eight Times Clock
14
TEST
I Test
15 NC – No Connect
16
RTIP
I Receive Analog Tip Input
17
RRING
I Receive Analog Ring Input
18
RVDD
– Receive Analog Positive Supply
19
RVSS
– Receive Analog Signal Ground
20
RVSS
– Receive Analog Signal Ground
21
MCLK
I Master Clock Input
22
XTALD
O Quartz Crystal Driver
23 NC – No Connect
24
RVSS
– Receive Analog Signal Ground
25
INT*
O Interrupt
26 NC – No Connect
27 NC – No Connect
28 NC – No Connect
29
TTIP
O Transmit Analog Tip Output
30
TVSS
– Transmit Analog Signal Ground
31
TVDD
– Transmit Analog Positive Supply
32
TRING
O Transmit Analog Ring Output
33
TCHBLK
O Transmit Channel Block
34
TLCLK
O Transmit Link Clock
35
TLINK
I Transmit Link Data
36 CI I Carry In
37
TSYNC
I/O Transmit Sync
38
TPOSI
I Transmit Positive Data Input
39
TNEGI
I Transmit Negative Data Input
40
TCLKI
I Transmit Clock Input
41
TCLKO
O Transmit Clock Output
42
TNEGO
O Transmit Negative Data Output
43
TPOSO
O Transmit Positive Data Output
Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER (cont.)
PIN
SYMBOL
TYPE DESCRIPTION
44
DVDD
– Digital Positive Supply
45
DVSS
– Digital Signal Ground
46
TCLK
I Transmit Clock
47
TSER
I Transmit Serial Data
48
TSIG
I Transmit Signaling Input
49
TESO
O Transmit Elastic Store Output
11 of 137
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS21552LN.PDF ] | |
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