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DS2154LN Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2154LN
Beschreibung Enhanced E1 Single Chip Transceiver
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 30 Seiten
DS2154LN Datasheet, Funktion
www.dalsemi.com
DS2154
Enhanced E1 Single Chip Transceiver
FEATURES
Complete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionality
Onboard long- and short-haul line interface for
clock/data recovery and waveshaping
32-bit or 128-bit crystal-less jitter attenuator
Generates line build outs for both 120=and
75=lines
Frames to FAS, CAS, and CRC4 formats
Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz
8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
Extracts and inserts CAS signaling
Detects and generates Remote and AIS alarms
Programmable output clocks for Fractional E1,
H0, and H12 applications
Fully independent transmit and receive
functionality
Full access to both Si and Sa bits aligned with
CRC multiframe
Four separate loopbacks for testing functions
Large counters for bipolar and code violations,
CRC4 codeword errors, FAS errors, and E bits
Pin compatible with DS2152 T1 Enhanced Single-
Chip Transceiver
5V supply; low power CMOS
100-pin 14mm2 body LQFP package
PACKAGE OUTLINE
1
ORDERING INFORMATION
DS2154L
(0°C to 70°C)
DS2154LN
(-40°C to +85°C)
DESCRIPTION
The DS2154 Enhanced Single-Chip Transceiver (ESCT) contains all of the necessary functions for
connection to E1 lines. The device is an upward compatible version of the DS2153 Single-Chip
Transceiver. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2154 automatically adjusts to E1 22AWG (0.6 mm) twisted-pair cables from 0 to
over 2 km in length. The device can generate the necessary G.703 waveshapes for both 75-ohm coax and
120-ohm twisted cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be
placed in either the transmit or receive data paths. The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling
data, Si, and Sa bit information. The device contains a set of internal registers which the user can access
to control the operation of the unit. Quick access via the parallel control port allows a single controller to
handle many E1 lines. The device fully meets all of the latest E1 specifications including ITU G.703,
G.704, G.706, G.823, G.932, and I.431 as well as ETS 300 011, 300 233, 300 166, TBR 12 and TBR 13.
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DS2154LN Datasheet, Funktion
DS2154
FUNCTIONAL DESCRIPTION
The analog AMI/HDB3 waveform off of the E1 line is transformer coupled into the RRING and RTIP
pins of the DS2154. The device recovers clock and data from the analog signal and passes it through the
jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the
framing/multiframe pattern. The DS2154 contains an active filter that reconstructs the analog received
signal for the non-linear losses that occur in transmission. The device has a usable receive sensitivity of 0
dB to -43 dB which allows the device to operate on cables over 2 km in length. The receive side framer
locates the FAS frame and CRC and CAS multiframe boundaries as well as detects incoming alarms
including, carrier loss, loss of synchronization, AIS, and Remote Alarm. If needed, the receive side elastic
store can be enabled in order to absorb the phase and frequency differences between the recovered E1
data stream and an asynchronous backplane clock which is provided at the RSYSCLK input. The clock
applied at the RSYSCLK input can be either a 2.048 MHz clock or a 1.544 MHz clock. The RSYSCLK
can also be a bursty clock with speeds up to 8.192 MHz.
The transmit side of the DS2154 is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission. Once the data stream has been prepared for transmission, it is sent via the jitter
attenuation mux to the waveshaping and line driver functions. The DS2154 will drive the E1 line from the
TTIP and TRING pins via a coupling transformer. The line driver can handle both 75=and 120=lines
and it has options for high return loss applications. The line driver contains a current limiter that will
restrict the maximum current into a 1=load to less than 50 mA (rms).
READER’S NOTE
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
timeslots in an E1 systems which are number 0 to 31. Timeslot 0 is transmitted first and received first.
These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is
identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made
up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS Frame Alignment Signal
CAS Channel Associated Signaling
MF Multiframe
Si International bits
CRC4
CCS
Sa
E-bit
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
CRC4 Error bits
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DS2154LN pdf, datenblatt
DS2154
Receive Sync [RSYNC]. An extracted pulse, one RCLK wide, is output at this pin which identifies either
frame or CAS/CRC multiframe boundaries. If the receive side elastic store is enabled, then this pin can be
enabled to be an input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is
applied.
Receive Frame Sync [RFSYNC]. An extracted 8 kHz pulse, one RCLK wide, is output at this pin which
identifies frame boundaries.
Receive Multiframe Sync [RMSYNC]. An extracted pulse, one RSYSCLK wide, is output at this pin
which identifies multiframe boundaries. If the receive side elastic store is disabled, then this output will
output multiframe boundaries associated with RCLK.
Receive Data [RDATA]. Updated on the rising edge of RCLK with the data out of the receive side
framer.
Receive System Clock [RSYSCLK]. 1.544 MHz or 2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications that do not use the elastic store. Can be burst at
rates up to 8.192 MHz.
Receive Signaling Output [RSIG]. Outputs signaling bits in a PCM format. Updated on rising edges of
RCLK when the receive side elastic store is disabled. Updated on the rising edges of RSYSCLK when the
receive side elastic store is enabled. See Section 13 for timing examples.
Receive Loss of Sync / Loss of Transmit Clock [RLOS/LOTC]. A dual function output that is
controlled by the TCR2.0 control bit. This pin can be programmed to either toggle high when the
synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been
toggled for 5 µs.
Receive Carrier Loss [RCL]. Set high when the line interface detects a loss of carrier. [Note: a test
mode exists to allow the DS2154 to detect carrier loss at RPOSI and RNEGI in place of detection at RTIP
and RRING].
Receive Signaling Freeze [RSIGF]. Set high when the signaling data is frozen via either automatic or
manual intervention. Used to alert downstream equipment of the condition.
8 MHz Clock [8MCLK]. 8.192 MHz output clock that is referenced to the clock that is output at the
RCLK pin.
Receive Positive Data Output [RPOSO]. Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output [RNEGO]. Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RNEGI.
Receive Clock Output [RCLKO]. Buffered recovered clock from the E1 line. This pin is normally tied
to RCLKI.
Receive Positive Data Input [RPOSI]. Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RPOSO by tying the LIUC pin high.
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