Datenblatt-pdf.com


DS2152LN Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS2152LN
Beschreibung Enhanced T1 Single-Chip Transceiver
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 30 Seiten
DS2152LN Datasheet, Funktion
www.dalsemi.com
DS2152
Enhanced T1 Single-Chip Transceiver
FEATURES
§ Complete DS1/ISDN-PRI transceiver
functionality
§ Line interface can handle both long and short haul
trunks
§ 32-bit or 128-bit crystal-less jitter attenuator
§ Generates DSX-1 and CSU line build outs
§ Frames to D4, ESF, and SLC-96R formats
§ Dual onboard two-frame elastic store slip buffers
that can connect to asynchronous backplanes up to
8.192 MHz
§ 8-bit parallel control port that can be used directly
on either multiplexed or non-multiplexed buses
(Intel or Motorola)
§ Extracts and inserts robbed-bit signaling
§ Detects and generates yellow (RAI) and blue
(AIS) alarms
§ Programmable output clocks for Fractional T1
§ Fully independent transmit and receive
functionality
§ Integral HDLC controller with 16-byte buffers for
the FDL
§ Generates and detects in-band loop codes from 1
to 8 bits in length including CSU loop codes
§ Contains ANSI 1's density monitor and enforcer
§ Large path and line error counters including BPV,
CV, CRC6, and framing bit errors
§ Pin compatible with DS2154 E1 Enhanced Single-
Chip Transceiver
§ 5V supply; low power CMOS
§ 100-pin 14mm2 body LQFP package
PIN ASSIGNMENT
1
ORDERING INFORMATION
DS2152L
(0°C to 70°C)
DS2152LN
(-40°C to +85°C)
DESCRIPTION
The DS2152 T1 Enhanced Single-Chip Transceiver contains all of the necessary functions for connection
to T1 lines, whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build outs as well as CSU line build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It
is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set
of internal registers which the user can access and control the operation of the unit. Quick access via the
parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the
latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (12-90),
AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431.
1 of 94
092299






DS2152LN Datasheet, Funktion
DS2152 ENHANCED T1 SINGLE-CHIP TRANSCEIVER Figure 1-1
DS2152
6 of 93

6 Page









DS2152LN pdf, datenblatt
DS2152
Receive Positive Data Output [RPOSO]. Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RPOSI.
Receive Negative Data Output [RNEGO]. Updated on the rising edge of RCLKO with the bipolar data
out of the line interface. This pin is normally tied to RNEGI.
Receive Clock Output [RCLKO]. Buffered recovered clock from the T1 line. This pin is normally tied
to RCLKI.
Receive Positive Data Input [RPOSI]. Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RPOSO by tying the LIUC pin high.
Receive Negative Data Input [RNEGI]. Sampled on the falling edge of RCLKI for data to be clocked
through the receive side framer. RPOSI and RNEGI can be tied together for a NRZ interface. Can be
internally connected to RNEGO by tying the LIUC pin high.
Receive Clock Input [RCLKI]. Clock used to clock data through the receive side framer. This pin is
normally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high.
PARALLEL CONTROL PORT PINS
Interrupt [INT]. Flags host controller during conditions and change of conditions defined in the Status
Registers 1 and 2 and the FDL Status Register. Active low, open drain output.
3-State Control [Test]. Set high to 3-state all output and I/O pins (including the parallel control port). Set
low for normal operation. Useful in board-level testing.
Bus Operation [MUX]. Set low to select non-multiplexed bus operation. Set high to select multiplexed
bus operation.
Data Bus [D0 to D7] or Address/Data Bus [AD0 to AD7]. In non-multiplexed bus operation (MUX =
0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed
address/data bus.
Address Bus [A0 to A6]. In non-multiplexed bus operation (MUX = 0), serves as the address bus. In
multiplexed bus operation (MUX = 1), these pins are not used and should be tied low.
Bus Type Select [BTS]. Strap high to select Motorola bus timing; strap low to select Intel bus timing.
This pin controls the function of the RD ( DS ), ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these
pins assume the function listed in parenthesis ().
Read Input [ RD ] (Data Strobe [ DS ]). RD and DS are active low signals when MUX=1. DS is active
high when MUX = 0. See bus timing diagrams.
Chip Select [ CS ]. Must be low to read or write to the device. CS is an active low signal.
A7 or Address Latch Enable [ALE] (Address Strobe [AS]). In non-multiplexed bus operation (MUX =
0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus
on a positive-going edge.
12 of 93

12 Page





SeitenGesamt 30 Seiten
PDF Download[ DS2152LN Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
DS2152LEnhanced T1 Single-Chip TransceiverDallas Semiconducotr
Dallas Semiconducotr
DS2152LNEnhanced T1 Single-Chip TransceiverDallas Semiconducotr
Dallas Semiconducotr

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche