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PDF DS2151 Data sheet ( Hoja de datos )
| Número de pieza | DS2151 | |
| Descripción | T1 Single-Chip Transceiver | |
| Fabricantes | Dallas Semiconducotr | |
| Logotipo |  |
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FEATURES
§ Complete DS1/ISDN-PRI transceiver
functionality
§ Line interface can handle both long- and
short-haul trunks
§ 32-bit or 128-bit jitter attenuator
§ Generates DSX-1 and CSU line build outs
§ Frames to D4, ESF, and SLC-96R formats
§ Dual onboard two-frame elastic store slip
buffers that connect to backplanes up to 8.192
MHz
§ 8-bit parallel control port that can be used on
either multiplexed or non-multiplexed buses
§ Extracts and inserts Robbed-Bit signaling
§ Detects and generates yellow and blue alarms
§ Programmable output clocks for Fractional T1
§ Fully independent transmit and receive
functionality
§ Onboard FDL support circuitry
§ Generates and detects CSU loop codes
§ Contains ANSI one’s density monitor and
enforcer
§ Large path and line error counters including
BPV, CV, CRC6, and framing bit errors
§ Pin compatible with DS2153Q E1 Single-
Chip Transceiver
§ 5V supply; low power CMOS
§ Industrial grade version (-40°C to +85°C)
available (DS2151QN)
DS2151Q
T1 Single-Chip Transceiver
PIN ASSIGNMENT
FUNCTIONAL BLOCKS
PARALLEL CONTROL
PORT
Dallas
DS2151Q
T1SCT
ACTUAL SIZE OF 44-PIN PLCC
ALE
WR
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
7
8
9
10
11
12
13
14
15
16
17
39 TSER
38 TCLK
37 DVDD
36 TSYNC
35 TLINK
34 TLCLK
33 TCHBLK
32 TRING
31 TVDD
30 TVSS
29 TTIP
DESCRIPTION
The DS2151Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection
to T1 lines whether they be DS-1 long haul or DSX-1 short haul. The clock recovery circuitry
automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both
DSX-1 line build outs as well as CSU build outs of -7.5 dB, -15 dB, and -22.5 dB. The onboard jitter
attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data
paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms.
It is also used for extracting and inserting Robbed-Bit signaling data and FDL data. The device contains
a set of 64 8-bit internal registers which the user can access to control the operation of the unit. Quick
access via the parallel control port allows a single micro to handle many T1 lines. The device fully meets
all of the latest T1 specifications including ANSI T1.403-199X, AT&T TR 62411 (12-90), and ITU
G.703, G.704, G.706, G.823, and I.431.
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081099
1 page  
DS2151Q
PIN SYMBOL TYPE
DESCRIPTION
19 ACLKI
20 BTS
I Alternate Clock Input. Upon a receive carrier loss, the clock applied at
this pin (normally 1.544 MHz) will be routed to the RCLK pin. If no
clock is routed to this pin, then it should be tied to DVSS VIA A1K Ohm
RESISTOR.
I Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the RD (DS),
21 RTIP
22 RRING
ALE(AS), and WR (R/ W ) pins. If BTS=1, then these pins assume the
function listed in parenthesis ().
- Receive Tip and Ring. Analog inputs for clock recovery circuitry;
connects to a 1:1 transformer (see Section 12 for details).
23 RVDD
24 RVSS
25 XTAL1
26 XTAL2
- Receive Analog Positive Supply. 5.0 volts. Should be tied to DVDD
and TVDD pins.
- Receive Signal Ground. 0.0 volts. Should be tied to local ground plane
- Crystal Connections. A pullable 6.176 MHz crystal must be applied to
these pins. See Section 12 for crystal specifications.
27 INT1
28 INT2
29 TTIP
30 TVSS
31 TVDD
32 TRING
33 TCHBLK
34 TLCLK
35 TLINK
36 TSYNC
37 DVDD
O Receive Alarm Interrupt 1. Flags host controller during alarm
conditions defined in Status Register 1. Active low, open drain output.
O Receive Alarm Interrupt 2. Flags host controller during conditions
defined in Status Register 2. Active low, open drain output.
- Transmit Tip. Analog line driver output; connects to a step-up
transformer (see Section 12 for details).
- Transmit Signal Ground. 0.0 volts. Should be tied to local ground
plane.
- Transmit Analog Positive Supply. 5.0 volts. Should be tied to DVDD
and RVDD pins.
- Transmit Ring. Analog line driver outputs; connects to a step-up
transformer (see Section 12 for details).
O Transmit Channel Block. A user programmable output that can be
forced high or low during any of the 24 T1 channels. Useful for blocking
clocks to a serial UART or LAPD controller in applications where not all
T1 channels are used such as Fractional T1, 384k bps service, 768k bps,
or ISDN-PRI. Also useful for locating individual channels in drop-and-
insert applications. See Section 13 for timing details.
O Transmit Link Clock. 4 kHz or 2 kHz (ZBTSI) demand clock for the
TLINK input. See Section 13 for timing details.
I Transmit Link Data. If enabled via TCR1.2, this pin will be sampled
during the F-bit time on the falling edge of TCLK for data insertion into
either the FDL stream (ESF) or the Fs bit position (D4) or the Z-bit
position (ZBTSI). See Section 13 for timing details.
I/O Transmit Sync. A pulse at this pin will establish either frame or
multiframe boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can
be programmed to output either a frame or multiframe pulse at this pin. If
this pin is set to output pulses at frame boundaries, it can also be set via
TCR2.4 to output double-wide pulses at signaling frames. See Section 13
for timing details.
- Digital Positive Supply. 5.0 volts. Should be tied to RVDD and TVDD
pins.
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5 Page 
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)
(MSB)
TEST1 TEST0 TZBTSI TSDW
TSM
TSIO
TD4YM
DS2151Q
(LSB)
B7ZS
SYMBOL
TEST1
POSITION NAME AND DESCRIPTION
TCR2.7 Test Mode Bit 1 for Output Pins. See Table 3-1.
TEST0
TCR2.6 Test Mode Bit 0 for Output Pins. See Table 3-1.
TZBTSI
TCR2.5
Transmit Side ZBTSI Enable.
0=ZBTSI disabled
1=ZBTSI enabled
TSDW
TCR2.4
TSYNC Double-Wide. (note: this bit must be set to 0 when
TCR2.3=1 or when TCR2.2=0)
0=do not pulse double-wide in signaling frames
1=do pulse double-wide in signaling frames
TSM
TCR2.3
TSYNC Mode Select.
0=frame mode (see the timing in Section 13)
1=multiframe mode (see the timing in Section 13)
TSIO
TCR2.2
TSYNC I/O Select.
0=TSYNC is an input
1=TSYNC is an output
TD4YM
TCR2.1
Transmit Side D4 Yellow Alarm Select.
0=0s in bit 2 of all channels
1=a 1 in the S-bit position of frame 12
B7ZS
XTCR2.0
Bit 7 0 Suppression Enable.
0=no stuffing occurs
1=Bit 7 force to a 1 in channels with all 0s
OUTPUT PIN TEST MODES Table 3-1
TEST1
TEST0
EFFECT ON OUTPUT PINS
0 0 operate normally
0 1 force all output pins 3-state (including all I/O pins and parallel port pins)
1 0 force all output pins low (including all I/O pins except parallel port pins)
1 1 force all output pins high (including all I/O pins except parallel port pins)
11 of 51
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS2151.PDF ] | |
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