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DS21448LN Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS21448LN
Beschreibung 3.3V E1/T1/J1 Quad Line Interface
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 60 Seiten
DS21448LN Datasheet, Funktion
DS21448
3.3V E1/T1/J1 Quad Line Interface
www.maxim-ic.com
GENERAL DESCRIPTION
The DS21448 is a quad-port E1 or T1 line interface
unit (LIU) for short-haul and long-haul applications. It
incorporates four independent transmitters and four
independent receivers in a single 144-pin PBGA or
128-pin LQFP package.
The transmit drivers generate the necessary G.703
E1 waveshapes in 75W or 120W applications and the
DSX-1 or CSU line build-outs of 0dB, -7.5dB, -15dB,
and -22.5dB for T1 applications.
The DS21448 has a usable receiver sensitivity of
0 to -43dB for E1 applications and 0 to -36dB for T1
that allows it to operate on 0.63mm (22AWG) cables
up to 2.5km (E1) and 6000ft (T1) in length. The user
has the option to use internal receive termination,
software selectable for 75W, 100W, and 120W
applications, or external termination.
The on-board crystal-less jitter attenuator can be
placed in either the transmit or the receive data path,
and requires only a 2.048MHz MCLK for both E1 and
T1 applications (with the option of using a 1.544MHz
MCLK in T1 applications).
The DS21448 has diagnostic capabilities such as
loopbacks and PRBS pattern generation and
detection. 16-bit loop-up and loop-down codes can
be generated and detected. A single input pin can
power down all transmitters to allow the
implementation of hitless protection switching (HPS)
for 1+1 redundancy without the use of relays.
The device can be controlled through an 8-bit parallel
port (muxed or nonmuxed) or a serial port, and it can
be used in hardware mode. A standard boundary
scan interface supports board-level testing.
APPLICATIONS
Integrated Multiservice Access Platforms
T1/E1 Cross-Connects, Multiplexers, and Channel
Banks
Central-Office Switches and PBX Interfaces
T1/E1 LAN/WAN Routers
Wireless Base Stations
FEATURES
§ Four Complete E1, T1, or J1 LIUs
§ Supports Long- and Short-Haul Trunks
§ Internal Software-Selectable Receive-Side
Termination for 75W/100W/120W
§ 3.3V Power Supply
§ 32-Bit or 128-Bit Crystal-Less Jitter Attenuator
Requires Only a 2.048MHz Master Clock for E1
and T1, with the Option to Use 1.544MHz for T1
§ Generates the Appropriate Line Build-Outs With
and Without Return Loss for E1, and DSX-1 and
CSU Line Build-Outs for T1
§ AMI, HDB3, and B8ZS Encoding/Decoding
§ 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
Clock Output Synthesized to Recovered Clock
§ Programmable Monitor Mode for Receiver
§ Loopbacks and PRBS Pattern Generation/
Detection with Output for Received Errors
§ Generates/Detects In-Band Loop Codes, 1 to 16
Bits, Including CSU Loop Codes
§ 8-Bit Parallel or Serial Interface with Optional
Hardware Mode
§ Muxed and Nonmuxed Parallel Bus Supports
Intel or Motorola
§ Detects/Generates Blue (AIS) Alarms
§ NRZ/Bipolar Interface for Tx/Rx Data I/O
§ Transmit Open-Circuit Detection
§ Receive Carrier Loss (RCL) Indication (G.775)
§ High-Z State for TTIP and TRING
§ 50mARMS Transmit Current Limiter
§ JTAG Boundary Scan Test Port per IEEE 1149.1
§ Meets Latest E1 and T1 Specifications Including
ANSI.403-1999, ANSI T1.408, AT&T TR 62411,
ITU G.703, G.704, G.706, G.736, G.775, G.823,
I.431, O.151, O.161, ETSI ETS 300 166,
JTG.703, JTI.431, TBR12, TBR13, and CTR4
ORDERING INFORMATION
PART
TEMP RANGE
VOLTAGE
(V)
DS21448
0°C to +70°C
3.3
DS21448N -40°C to +85°C
3.3
DS21448L
0°C to +70°C
3.3
DS21448LN -40°C to +85°C
3.3
Pin Configurations appear in Section 11.
PIN-
PACKAGE
144 BGA
144 BGA
128 LQFP
128 LQFP
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 012104






DS21448LN Datasheet, Funktion
Figure 1-2. Receive Logic Detail
DS21448 3.3V T1/E1/J1 Quad Line Interface
FROM
REMOTE
LOOPBACK
ROUTED TO
ALL BLOCKS
CLOCK
INVERT
CCR2.0
B8ZS/HDB3
DECODER
NRZ DATA
BPV/CV/EXZ
RCLK
MUX
RPOS
RNEG
4 OR 8 ZERO DETECT
16 ZERO DETECT
RIR1.7
RIR1.6
CCR2.3
CCR6.2/ RIR1.5
CCR6.0/
CCR6.1
ALL-ONES
DETECTOR
LOOP CODE
DETECTOR
SR.4 RIR1.3 SR.6 SR.7
PRBS
DETECTOR
SR.0
CCR1.4
CCR1.6 PBEO
MUX
CCR6.0
16-BIT ERROR
COUNTER (ECR)
Figure 1-3. Transmit Logic Detail
CCR1.6
CCR3.3 CCR3.4
TO REMOTE
LOOPBACK
CCR3.1
OR
GATE
1
BPV
INSERT
MUX
CCR2.2
B8ZS/
HDB3
CODER
CCR3.0
LOGIC
ERROR
INSERT
MUX
PRBS
GENERATOR
LOOP CODE
GENERATOR
OR
GATE
0
0
MUX
1
RCLK
ROUTED TO CCR1.1
ALL BLOCKS
0
MUX
1
OR
GATE
AND
GATE
JACLK
(FROM MCLK)
LOSS-OF-TRANSMIT
CLOCK DETECT
CCR1.2
CCR1.0
TO LOTC OUTPUT PIN SR.5
CLOCK
INVERT
CCR2.1
TPOS
TNEG
TCLK
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DS21448LN pdf, datenblatt
DS21448 3.3V T1/E1/J1 Quad Line Interface
PIN
CES
TPD
TX0/TX1
LOOP0/LOOP1
MM0/MM1
RT1/RT0
TEST
HRST
MCLK
BIS0/BIS1
EGL1–EGL4
PBEO1–PBEO4
RCL1–RCL4
RTIP1–RTIP4
RRING1–RRING4
BPCLK1–BPCLK4
TTIP1–TTIP4
TRING1–TRING4
RPOS1–RPOS4
RNEG1–RNEG4
RCLK1–RCLK4
TPOS1–TPOS4
TNEG1–TNEG4
TCLK1–TCLK4
JTRST
JTMS
JTCLK
JTDI
JTDO
VSM
TVDD1–TVDD4
VDD1–VDD4
I/O FUNCTION
Receive and Transmit Clock Select. Selects which RCLK edge to update RPOS and RNEG and
I
which TCLK edge to sample TPOS and TNEG. CES combines TCES and RCES.
0 = update RPOS/RNEG on rising edge of RCLK; sample TPOS/TNEG on falling edge of TCLK
1 = update RPOS/RNEG on falling edge of RCLK; sample TPOS/TNEG on rising edge of TCLK
Transmit Power-Down
I 0 = normal transmitter operation
1 = powers down the transmitter and tri-states TTIP and TRING pins
I
Transmit Data Source Select Bits 0 and 1. These inputs determine the source of the transmit
data (Table 4-B).
I Loopback Select Bits 0 and 1. These inputs determine the active loopback mode (Table 4-A).
I
Monitor Mode Select Bits 0 and 1. These inputs determine if the receive equalizer is in a monitor
mode (Table 4-D).
I
Receive LIU Termination Select Bits 0 and 1. These inputs determine the receive termination
(Table 4-E).
I
Tri-State Control. Set high to tri-state all outputs and I/O pins (including the parallel control port).
Set low for normal operation. Useful in board-level testing.
I
Hardware Reset. Bringing HRST low resets the DS21448, setting all control bits to the all-zero
default state.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This
I clock is used internally for both clock/data recovery and for jitter attenuation. A T1 1.544MHz
clock source is optional (Note 1). See Table 4-F for details.
I Bus Interface Select Bit 0 and 1. Used to select bus interface option (Table 2-A).
I
Receive Equalizer Gain-Limit Select. These bits control the sensitivity of the receive equalizers
(Table 4-C).
PRBS Bit-Error Output. The receiver constantly searches for a 215 - 1 PRBS (ETS = 0) or a
QRSS PRBS (ETS = 1). The pattern is chosen automatically by the value of the ETS pin. It
O remains high if it is out of synchronization with the PRBS pattern. It goes low when synchronized
to the PRBS pattern. Any errors in the received pattern after synchronization cause a positive-
going pulse (with same period as E1 or T1 clock) synchronous with RCLK.
O Receive Carrier Loss. An output that toggles high during a receive carrier loss.
I Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a
I 1:1 transformer to the line. See Section 7 for details.
O Backplane Clock. A 16.384MHz clock output that is referenced to RCLK.
O
Transmit Tip and Ring. Analog line-driver outputs. These pins connect through a step-up
transformer to the line. See Section 7 for details.
Receive Positive Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of
O
RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on
RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with
RCLK at RNEG.
Receive Negative Data. Updated on the rising edge (CES = 0) or the falling edge (CES = 1) of
O
RCLK with bipolar data out of the line interface. In NRZ mode (NRZE = 1), data is output on
RPOS, and a received error (BPV, CV, or EXZ) causes a positive-going pulse synchronous with
RCLK at RNEG.
O
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of
signal at RTIP and RRING.
I
Transmit Positive Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of
TCLK for data to be transmitted out onto the line.
I
Transmit Negative Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of
TCLK for data to be transmitted out onto the line.
Transmit Clock. A 2.048MHz or 1.544MHz primary clock used to clock data through the transmit
I side formatter. It can be sourced internally by MCLK or RCLK. See Common Control Register 1
and Figure 1-3.
I JTAG Reset
I JTAG Mode Select
I JTAG Clock
I JTAG Data In
O JTAG Data Out
I Voltage Supply Mode (LQFP only). VSM should be wired low for correct operation.
– 3.3V, ±5% Transmitter Positive Supply
— 3.3V, ±5% Positive Supply
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