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DS21372TN Schematic ( PDF Datasheet ) - Dallas Semiconducotr

Teilenummer DS21372TN
Beschreibung 3.3V Bit Error Rate Tester BERT
Hersteller Dallas Semiconducotr
Logo Dallas Semiconducotr Logo 




Gesamt 21 Seiten
DS21372TN Datasheet, Funktion
DS21372
3.3V Bit Error Rate Tester (BERT)
www.dalsemi.com
FEATURES
Generates/detects digital bit patterns for
analyzing, evaluating and troubleshooting
digital communications systems
Operates at speeds from DC to 20 MHz
Programmable polynomial length and
feedback taps for generation of any other
pseudorandom pattern up to 32 bits in length
including: 26-1, 29-1, 211-1, 215-1, 220-1, 223-1,
and 232-1
Programmable user-defined pattern and
length for generation of any repetitive pattern
up to 32 bits in length
Large 32-bit error count and bit count
registers
Software programmable bit error insertion
Fully independent transmit and receive
sections
8-bit parallel control port
Detects test patterns with bit error rates up to
10-2
PIN ASSIGNMENT
TL
AD0
AD1
TEST
VSS
AD2
AD3
AD4
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 DS21372 21
5 32-PIN TQFP 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
RL
RLOS
LC
VSS
VDD
INT
WR(R/W)
ALE(AS)
ORDERING INFORMATION
DS21372T
(00 C to 700 C)
DS21372TN (-400 C to +850 C)
DESCRIPTION
The DS21372 Bit Error Rate Tester (BERT) is a software programmable test pattern generator, receiver,
and analyzer capable of meeting the most stringent error performance requirements of digital
transmission facilities. Two categories of test pattern generation (Pseudo-random and Repetitive)
conform to CCITT/ITU O.151, O.152, O.153, and O.161 standards. The DS21372 operates at clock rates
ranging from DC to 20 MHz. This wide range of operating frequency allows the DS21372 to be used in
existing and future test equipment, transmission facilities, switching equipment, multiplexers, DACs,
Routers, Bridges, CSUs, DSUs, and CPE equipment.
The DS21372 user-programmable pattern registers provide the unique ability to generate loopback
patterns required for T1, Fractional-T1, Smart Jack, and other test procedures. Hence the DS21372 can
initiate the loopback, run the test, check for errors, and finally deactivate the loopback.
The DS21372 consists of four functional blocks: the pattern generator, pattern detector, error counter, and
control interface. The DS21372 can be programmed to generate any pseudorandom pattern with length up
to 232-1 bits (see Table 5, Note 9) or any user programmable bit pattern from 1 to 32 bits in length. Logic
inputs can be used to configure the DS21372 for applications requiring gap clocking such as Fractional-
T1, Switched-56, DDS, normal framing requirements, and per-channel test procedures. In addition, the
DS21372 can insert single or 10-1 to 10-7 bit errors to verify equipment operation and connectivity.
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DS21372TN Datasheet, Funktion
DS21372
2. PARALLEL CONTROL INTERFACE
The DS21372 is controlled via a multiplexed bi-directional address/data bus by an external
microcontroller or microprocessor. The DS21372 can operate with either Intel or Motorola bus timing
configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will
be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.
Electrical Characteristics for more details. The multiplexed bus on the DS21372 saves pins because the
address information and data information share the same signal paths. The addresses are presented to the
pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of
the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS21372
latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during
the later portion of the DS or WR pulses. In a read cycle, the DS21372 outputs a byte of data during the
latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high
impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The
DS21372 can also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update
counters and load transmit and receive pattern registers. At slow clock rates, sufficient time must be
allowed for these port operations.
3. PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
(MSB)
PS31 PS30 PS29 PS28 PS27
PS23 PS22 PS21 PS20 PS19
PS15 PS14 PS13 PS12 PS11
PS7 PS6 PS5 PS4 PS3
PS26
PS18
PS10
PS2
PS25
PS17
PS9
PS1
(LSB)
PS24
PS16
PS8
PS0
PSR3 (addr.=00 Hex)
PSR2 (addr.=01 Hex)
PSR1 (addr.=02 Hex)
PSR0 (addr.=03 Hex)
4. PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
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DS21372TN pdf, datenblatt
BIT COUNT REGISTERS
(MSB)
BC31 BC30 BC29 BC28
BC23 BC22 BC21 BC20
BC15 BC14 BC13 BC12
BC7 BC6 BC5 BC4
BC27
BC19
BC11
BC3
BC26
BC18
BC10
BC2
BC25
BC17
BC9
BC1
DS21372
(LSB)
BC24
BC16
BC8
BC0
BCR3 (addr.=08 Hex)
BCR2 (addr.=09 Hex)
BCR1 (addr.=0A Hex)
BCR0 (addr.=0B Hex)
9. BIT ERROR COUNT REGISTERS
The Bit Error Count Registers (BECR3 to BECR0) comprise a 32-bit count of bits received in error at
RDATA. The bit error counter is disabled during loss of SYNC. BEC31 is the MSB of the 32-bit count.
The Status Register bit BECOF is set when this 32-bit register overflows. Upon an overflow condition,
the user must clear the BECR by either toggling the LC bit or pin. The DS21372 latches the bit error
count into the BECR registers and clears the internal bit error count when either the PCR.4 bit or the LC
input pin toggles from low to high. The bit count (available via the BCRs) and bit error count are used by
an external processor to compute the BER performance on a loop or channel basis.
BIT ERROR COUNT REGISTERS
(MSB)
BEC31 BEC30 BEC29 BEC28 BEC27
BEC23 BEC22 BEC21 BEC20 BEC19
BEC15 BEC14 BEC13 BEC12 BEC11
BEC7 BEC6 BEC5 BEC4 BEC3
BEC26
BEC18
BEC10
BEC2
BEC25
BEC17
BEC9
BEC1
(LSB)
BEC24
BEC16
BEC8
BEC0
BECR3 (addr.=0C Hex)
BECR2 (addr.=0D Hex)
BECR1 (addr.=0E Hex)
BECR0 (addr.=0F Hex)
10. PATTERN RECEIVE REGISTERS
The Pattern Receive Register (PRR) provides access to the data patterns received at RDATA. The
operation of these registers depends on the synchronization status of the DS21372. Asserting the RL bit
(PCR.3) or pin during an out-of -sync condition (SR.0 = 0) will latch the previous 32 bits of data received
at RDATA into the PRR registers. When the DS21372 is in sync (SR.0 = 1) asserting RL will latch the
pattern that to which the device has established synchronization. Since the receiver has no knowledge of
the start or end of the pattern, the data in the PRR registers will have no particular alignment. As an
example, if the receiver has synchronized to the pattern 00100110, PRR1 may report 10011000,
11000100 or any rotation thereof. Once synchronization is established, bit errors cannot be viewed in the
PRR registers.
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